[llvm] [AMDGPU] Add legalizer rule support for AMDGPU's regbank fminimumnum and fmaximumnum (PR #192719)
Jasmine Tang via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 12:14:46 PDT 2026
https://github.com/badumbatish created https://github.com/llvm/llvm-project/pull/192719
None
>From e8719cfee25fba32f64bfdcf79b38c3cf1c316bb Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Fri, 17 Apr 2026 12:10:06 -0700
Subject: [PATCH] [AMDGPU] Add legalizer rule support for AMDGPU's regbank
fminimumnum
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 10 +
.../GlobalISel/regbankselect-fminimumnum.mir | 364 ++++
llvm/test/CodeGen/AMDGPU/minimumnum.ll | 1699 +++++++++++++++++
3 files changed, 2073 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index d84640c682ad8..5131f5d111d79 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1446,6 +1446,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
+ addRulesForGOpcs({G_FMINIMUMNUM, G_FMAXIMUMNUM}, Standard)
+ .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}})
+ .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
+ .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
+ .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}});
+
addRulesForGOpcs({G_FPTRUNC})
.Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
.Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir
new file mode 100644
index 0000000000000..03ff508bbe8a6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir
@@ -0,0 +1,364 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -allow-unused-prefixes -check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -allow-unused-prefixes -check-prefixes=CHECK,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -allow-unused-prefixes -check-prefixes=CHECK,GFX12 %s
+
+---
+name: fminimumnum_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fminimumnum_s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMINIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMINIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fminimumnum_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fminimumnum_s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMINIMUMNUM [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMINIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMINIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fminimumnum_s32_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fminimumnum_s32_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fminimumnum_s32_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fminimumnum_s32_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fminimumnum_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-LABEL: name: fminimumnum_s64_s
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUMNUM]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = COPY $sgpr2_sgpr3
+ %2:_(s64) = G_FMINIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fminimumnum_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-LABEL: name: fminimumnum_s64_v
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUMNUM]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_FMINIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fmaximumnum_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMAXIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMAXIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fmaximumnum_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMAXIMUMNUM [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMAXIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMAXIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fmaximumnum_s32_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s32_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_s32_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s32_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-LABEL: name: fmaximumnum_s64_s
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUMNUM]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = COPY $sgpr2_sgpr3
+ %2:_(s64) = G_FMAXIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fmaximumnum_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-LABEL: name: fmaximumnum_s64_v
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUMNUM]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_FMAXIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fminimumnum_v2s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fminimumnum_v2s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $sgpr0
+ %1:_(<2 x s16>) = COPY $sgpr1
+ %2:_(<2 x s16>) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fminimumnum_v2s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fminimumnum_v2s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = COPY $vgpr1
+ %2:_(<2 x s16>) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_v2s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fmaximumnum_v2s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $sgpr0
+ %1:_(<2 x s16>) = COPY $sgpr1
+ %2:_(<2 x s16>) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_v2s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fmaximumnum_v2s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = COPY $vgpr1
+ %2:_(<2 x s16>) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
index 87f76bab79ed0..c957fffed7d56 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
@@ -32,6 +32,12 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-SDAG,GFX12-FAKE16-SDAG %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-GISEL,GFX12-FAKE16-GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-REGBANK,GFX11-FAKE16-REGBANK %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-REGBANK,GFX11-TRUE16-REGBANK %s
+
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-REGBANK,GFX12-FAKE16-REGBANK %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-REGBANK,GFX12-TRUE16-REGBANK %s
+
define half @v_minimumnum_f16(half %x, half %y) {
; GFX7-SDAG-LABEL: v_minimumnum_f16:
; GFX7-SDAG: ; %bb.0:
@@ -222,6 +228,50 @@ define half @v_minimumnum_f16(half %x, half %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -306,6 +356,38 @@ define half @v_minimumnum_f16_nnan(half %x, half %y) {
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -395,6 +477,46 @@ define half @v_minimumnum_f16_1.0(half %x) {
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_1.0:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, 1.0, v0
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_1.0:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, 1.0, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_1.0:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, 1.0, v0
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_1.0:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, 1.0, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half 1.0)
ret half %result
}
@@ -519,6 +641,26 @@ define float @v_minimumnum_f32(float %x, float %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -569,6 +711,22 @@ define float @v_minimumnum_f32_nnan(float %x, float %y) {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -699,6 +857,28 @@ define double @v_minimumnum_f64(double %x, double %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -749,6 +929,22 @@ define double @v_minimumnum_f64_nnan(double %x, double %y) {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -809,6 +1005,26 @@ define float @v_minimumnum_f32_1.0(float %x) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, 1.0, v0
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_1.0:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, 1.0, v0
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_1.0:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e32 v0, v0, v0
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, 1.0, v0
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float 1.0)
ret float %result
}
@@ -873,6 +1089,26 @@ define float @v_minimumnum_f32_rhs_not_snan(float %x, float %y) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_rhs_not_snan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_rhs_not_snan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%canon.y = call float @llvm.canonicalize.f32(float %y)
%result = call float @llvm.minimumnum.f32(float %x, float %canon.y)
ret float %result
@@ -938,6 +1174,26 @@ define float @v_minimumnum_f32_lhs_not_snan(float %x, float %y) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_lhs_not_snan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_lhs_not_snan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%canon.x = call float @llvm.canonicalize.f32(float %x)
%result = call float @llvm.minimumnum.f32(float %canon.x, float %y)
ret float %result
@@ -1003,6 +1259,26 @@ define float @v_minimumnum_f32_both_operands_not_snan(float %x, float %y) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_both_operands_not_snan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_both_operands_not_snan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%canon.x = call float @llvm.canonicalize.f32(float %x)
%canon.y = call float @llvm.canonicalize.f32(float %y)
%result = call float @llvm.minimumnum.f32(float %canon.x, float %canon.y)
@@ -1065,6 +1341,26 @@ define double @v_minimumnum_f64_1.0(double %x) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], 1.0, v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_1.0:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], 1.0
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_1.0:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], 1.0, v[0:1]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double 1.0)
ret double %result
}
@@ -1275,6 +1571,50 @@ define half @v_minimumnum_f16_v_s(half %x, half inreg %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_v_s:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v1, s0, s0
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_v_s:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.h, s0, s0
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_v_s:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v1, s0, s0
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_v_s:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.h, s0, s0
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -1485,6 +1825,60 @@ define half @v_minimumnum_f16_s_s(half inreg %x, half inreg %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_s_s:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v0, s0, s0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v1, s1, s1
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_s_s:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.l, s0, s0
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.h, s1, s1
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_s_s:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v0, s0, s0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v1, s1, s1
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-REGBANK-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_min_num_f16 s0, s0, s1
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-FAKE16-REGBANK-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_s_s:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.l, s0, s0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v1.l, s1, s1
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-REGBANK-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-TRUE16-REGBANK-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-TRUE16-REGBANK-NEXT: s_min_num_f16 s0, s0, s1
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-TRUE16-REGBANK-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -1631,6 +2025,28 @@ define float @v_minimumnum_f32_s_v(float inreg %x, float %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v1, v0
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_s_v:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, s0, s0
+; GFX11-REGBANK-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v1, v0
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_s_v:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, s0, s0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e32 v0, v0, v0
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v1, v0
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -1777,6 +2193,28 @@ define float @v_minimumnum_f32_v_s(float %x, float inreg %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_v_s:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, s0, s0
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_v_s:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e32 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, s0, s0
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -1923,6 +2361,33 @@ define float @v_minimumnum_f32_s_s(float inreg %x, float inreg %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_s_s:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v0, s0, s0
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, s1, s1
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_s_s:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v0, s0, s0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, s1, s1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-REGBANK-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-REGBANK-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-REGBANK-NEXT: s_min_num_f32 s0, s0, s1
+; GFX12-REGBANK-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-REGBANK-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -2030,6 +2495,28 @@ define double @v_minimumnum_f64_s_v(double inreg %x, double %y) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_s_v:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_s_v:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -2137,6 +2624,28 @@ define double @v_minimumnum_f64_v_s(double %x, double inreg %y) {
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_v_s:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_v_s:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -2283,6 +2792,28 @@ define double @v_minimumnum_f64_s_s(double inreg %x, double inreg %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_s_s:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], s[0:1], s[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], s[2:3], s[2:3]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_s_s:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e64 v[0:1], s[0:1], s[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e64 v[2:3], s[2:3], s[2:3]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -2413,6 +2944,28 @@ define float @v_minimumnum_f32_fabs_rhs(float %x, float %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_fabs_rhs:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, |v1|, |v1|
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_fabs_rhs:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e32 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%result = call float @llvm.minimumnum.f32(float %x, float %fabs.y)
ret float %result
@@ -2544,6 +3097,28 @@ define float @v_minimumnum_f32_fneg_fabs_rhs(float %x, float %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, -|v1|, -|v1|
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_fneg_fabs_rhs:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e32 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1|
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%fneg.fabs.y = fneg float %fabs.y
%result = call float @llvm.minimumnum.f32(float %x, float %fneg.fabs.y)
@@ -2676,6 +3251,28 @@ define float @v_minimumnum_f32_fabs(float %x, float %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_fabs:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v0, |v0|, |v0|
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, |v1|, |v1|
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_fabs:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v0, |v0|, |v0|
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, |v1|, |v1|
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
%result = call float @llvm.minimumnum.f32(float %fabs.x, float %fabs.y)
@@ -2808,6 +3405,28 @@ define float @v_minimumnum_f32_fneg(float %x, float %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_fneg:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v0, -v0, -v0
+; GFX11-REGBANK-NEXT: v_max_f32_e64 v1, -v1, -v1
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_fneg:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v0, -v0, -v0
+; GFX12-REGBANK-NEXT: v_max_num_f32_e64 v1, -v1, -v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg float %x
%fneg.y = fneg float %y
%result = call float @llvm.minimumnum.f32(float %fneg.x, float %fneg.y)
@@ -3004,6 +3623,50 @@ define half @v_minimumnum_f16_fabs_rhs(half %x, half %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v1, |v1|, |v1|
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fabs_rhs:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call half @llvm.fabs.f16(half %y)
%result = call half @llvm.minimumnum.f16(half %x, half %fabs.y)
ret half %result
@@ -3199,6 +3862,50 @@ define half @v_minimumnum_f16_fneg_fabs_rhs(half %x, half %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v1, -|v1|, -|v1|
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.h, -|v1.l|, -|v1.l|
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1|
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fneg_fabs_rhs:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.h, -|v1.l|, -|v1.l|
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call half @llvm.fabs.f16(half %y)
%fneg.fabs.y = fneg half %fabs.y
%result = call half @llvm.minimumnum.f16(half %x, half %fneg.fabs.y)
@@ -3395,6 +4102,50 @@ define half @v_minimumnum_f16_fabs(half %x, half %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fabs:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v0, |v0|, |v0|
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v1, |v1|, |v1|
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fabs:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fabs:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v0, |v0|, |v0|
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v1, |v1|, |v1|
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fabs:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.l, |v0.l|, |v0.l|
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.h, |v1.l|, |v1.l|
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call half @llvm.fabs.f16(half %x)
%fabs.y = call half @llvm.fabs.f16(half %y)
%result = call half @llvm.minimumnum.f16(half %fabs.x, half %fabs.y)
@@ -3591,6 +4342,50 @@ define half @v_minimumnum_f16_fneg(half %x, half %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fneg:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v0, -v0, -v0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e64 v1, -v1, -v1
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fneg:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.l, -v0.l, -v0.l
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e64 v0.h, -v1.l, -v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_fneg:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v0, -v0, -v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e64 v1, -v1, -v1
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_fneg:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.l, -v0.l, -v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e64 v0.h, -v1.l, -v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg half %x
%fneg.y = fneg half %y
%result = call half @llvm.minimumnum.f16(half %fneg.x, half %fneg.y)
@@ -3723,6 +4518,28 @@ define double @v_minimumnum_f64_fneg(double %x, double %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_fneg:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], -v[2:3], -v[2:3]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_fneg:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e64 v[0:1], -v[0:1], -v[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e64 v[2:3], -v[2:3], -v[2:3]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%fneg.x = fneg double %x
%fneg.y = fneg double %y
%result = call double @llvm.minimumnum.f64(double %fneg.x, double %fneg.y)
@@ -3899,6 +4716,28 @@ define <2 x half> @v_minimumnum_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -3987,6 +4826,22 @@ define <2 x half> @v_minimumnum_v2f16_nnan(<2 x half> %x, <2 x half> %y) {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f16_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f16_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -4199,6 +5054,34 @@ define <3 x half> @v_minimumnum_v3f16(<3 x half> %x, <3 x half> %y) {
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x half> @llvm.minimumnum.v3f16(<3 x half> %x, <3 x half> %y)
ret <3 x half> %result
}
@@ -4309,6 +5192,24 @@ define <3 x half> @v_minimumnum_v3f16_nnan(<3 x half> %x, <3 x half> %y) {
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f16_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f16_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <3 x half> @llvm.minimumnum.v3f16(<3 x half> %x, <3 x half> %y)
ret <3 x half> %result
}
@@ -4557,6 +5458,34 @@ define <4 x half> @v_minimumnum_v4f16(<4 x half> %x, <4 x half> %y) {
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %x, <4 x half> %y)
ret <4 x half> %result
}
@@ -4680,6 +5609,24 @@ define <4 x half> @v_minimumnum_v4f16_nnan(<4 x half> %x, <4 x half> %y) {
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f16_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f16_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <4 x half> @llvm.minimumnum.v4f16(<4 x half> %x, <4 x half> %y)
ret <4 x half> %result
}
@@ -5002,6 +5949,40 @@ define <6 x half> @v_minimumnum_v6f16(<6 x half> %x, <6 x half> %y) {
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v1, v1, v4
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v2, v2, v5
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v6f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v4, v4, v4
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v5, v5, v5
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v3
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v4
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v2, v2, v5
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v6f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v4, v4, v4
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v5, v5, v5
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v3
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v4
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v2, v2, v5
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x half> @llvm.minimumnum.v6f16(<6 x half> %x, <6 x half> %y)
ret <6 x half> %result
}
@@ -5398,6 +6379,46 @@ define <8 x half> @v_minimumnum_v8f16(<8 x half> %x, <8 x half> %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v3, v3, v7
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v8f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v4, v4, v4
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v5, v5, v5
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v6, v6, v6
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v7, v7, v7
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v4
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v5
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v2, v2, v6
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v3, v3, v7
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v8f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v4, v4, v4
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v5, v5, v5
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v6, v6, v6
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v7, v7, v7
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v4
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v5
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v2, v2, v6
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v3, v3, v7
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x half> @llvm.minimumnum.v8f16(<8 x half> %x, <8 x half> %y)
ret <8 x half> %result
}
@@ -6084,6 +7105,68 @@ define <16 x half> @v_minimumnum_v16f16(<16 x half> %x, <16 x half> %y) {
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v6, v6, v11
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v7, v7, v12
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v16f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v8, v8, v8
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v9, v9, v9
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v10, v10, v10
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v8
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v9
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v8, v11, v11
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v2, v2, v10
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v4, v4, v4
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v9, v12, v12
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v5, v5, v5
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v10, v13, v13
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v6, v6, v6
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v11, v14, v14
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v7, v7, v7
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v12, v15, v15
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v3, v3, v8
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v4, v4, v9
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v5, v5, v10
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v6, v6, v11
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v7, v7, v12
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v16f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v8, v8, v8
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v9, v9, v9
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v10, v10, v10
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v8
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v9
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v8, v11, v11
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v2, v2, v10
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v4, v4, v4
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v9, v12, v12
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v5, v5, v5
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v10, v13, v13
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v6, v6, v6
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v11, v14, v14
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v7, v7, v7
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v12, v15, v15
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v3, v3, v8
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v4, v4, v9
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v5, v5, v10
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v6, v6, v11
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v7, v7, v12
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x half> @llvm.minimumnum.v16f16(<16 x half> %x, <16 x half> %y)
ret <16 x half> %result
}
@@ -7435,6 +8518,122 @@ define <32 x half> @v_minimumnum_v32f16(<32 x half> %x, <32 x half> %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v15, v15, v16
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v32f16:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: scratch_load_b32 v31, off, s32
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v0, v0, v0
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v16, v16, v16
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v17, v17, v17
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v18, v18, v18
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v3, v3, v3
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v19, v19, v19
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v4, v4, v4
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v20, v20, v20
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v5, v5, v5
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v21, v21, v21
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v6, v6, v6
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v22, v22, v22
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v7, v7, v7
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v23, v23, v23
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v8, v8, v8
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v24, v24, v24
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v9, v9, v9
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v25, v25, v25
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v10, v10, v10
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v26, v26, v26
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v11, v11, v11
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v27, v27, v27
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v12, v12, v12
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v28, v28, v28
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v13, v13, v13
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v29, v29, v29
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v14, v14, v14
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v30, v30, v30
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v15, v15, v15
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v16
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v17
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v2, v2, v18
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v3, v3, v19
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v4, v4, v20
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v5, v5, v21
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v6, v6, v22
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v7, v7, v23
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v8, v8, v24
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v9, v9, v25
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v10, v10, v26
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v11, v11, v27
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v12, v12, v28
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v13, v13, v29
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v14, v14, v30
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_max_f16 v16, v31, v31
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v15, v15, v16
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v32f16:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: scratch_load_b32 v31, off, s32
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v16, v16, v16
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v17, v17, v17
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v18, v18, v18
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v19, v19, v19
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v4, v4, v4
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v20, v20, v20
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v5, v5, v5
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v21, v21, v21
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v6, v6, v6
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v22, v22, v22
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v7, v7, v7
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v23, v23, v23
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v8, v8, v8
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v24, v24, v24
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v9, v9, v9
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v25, v25, v25
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v10, v10, v10
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v26, v26, v26
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v11, v11, v11
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v27, v27, v27
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v12, v12, v12
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v28, v28, v28
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v13, v13, v13
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v29, v29, v29
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v14, v14, v14
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v30, v30, v30
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v15, v15, v15
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v16
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v17
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v2, v2, v18
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v3, v3, v19
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v4, v4, v20
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v5, v5, v21
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v6, v6, v22
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v7, v7, v23
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v8, v8, v24
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v9, v9, v25
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v10, v10, v26
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v11, v11, v27
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v12, v12, v28
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v13, v13, v29
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v14, v14, v30
+; GFX12-REGBANK-NEXT: s_wait_loadcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v16, v31, v31
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v15, v15, v16
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <32 x half> @llvm.minimumnum.v32f16(<32 x half> %x, <32 x half> %y)
ret <32 x half> %result
}
@@ -7589,6 +8788,28 @@ define <2 x float> @v_minimumnum_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f32:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f32:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x float> @llvm.minimumnum.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %result
}
@@ -7643,6 +8864,22 @@ define <2 x float> @v_minimumnum_v2f32_nnan(<2 x float> %x, <2 x float> %y) {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f32_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_min_f32 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f32_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v0, v0, v2 :: v_dual_min_num_f32 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <2 x float> @llvm.minimumnum.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %result
}
@@ -7833,6 +9070,32 @@ define <3 x float> @v_minimumnum_v3f32(<3 x float> %x, <3 x float> %y) {
; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v2, v2, v5
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f32:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v4, v4, v4
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v5, v5, v5
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v0, v0, v3 :: v_dual_min_f32 v1, v1, v4
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f32:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v4, v4, v4
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v5, v5, v5
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x float> @llvm.minimumnum.v3f32(<3 x float> %x, <3 x float> %y)
ret <3 x float> %result
}
@@ -7894,6 +9157,24 @@ define <3 x float> @v_minimumnum_v3f32_nnan(<3 x float> %x, <3 x float> %y) {
; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
; GFX12-NEXT: v_min_num_f32_e32 v2, v2, v5
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f32_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v0, v0, v3 :: v_dual_min_f32 v1, v1, v4
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f32_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v0, v0, v3 :: v_dual_min_num_f32 v1, v1, v4
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <3 x float> @llvm.minimumnum.v3f32(<3 x float> %x, <3 x float> %y)
ret <3 x float> %result
}
@@ -8114,6 +9395,34 @@ define <4 x float> @v_minimumnum_v4f32(<4 x float> %x, <4 x float> %y) {
; GFX12-GISEL-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
; GFX12-GISEL-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f32:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v5, v5, v5
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v3, v3, v3
+; GFX11-REGBANK-NEXT: v_dual_max_f32 v6, v6, v6 :: v_dual_max_f32 v7, v7, v7
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v0, v0, v4 :: v_dual_min_f32 v1, v1, v5
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v2, v2, v6 :: v_dual_min_f32 v3, v3, v7
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f32:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v4, v4, v4 :: v_dual_max_num_f32 v5, v5, v5
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v2, v2, v2 :: v_dual_max_num_f32 v3, v3, v3
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v6, v6, v6 :: v_dual_max_num_f32 v7, v7, v7
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x float> @llvm.minimumnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %result
}
@@ -8179,6 +9488,24 @@ define <4 x float> @v_minimumnum_v4f32_nnan(<4 x float> %x, <4 x float> %y) {
; GFX12-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
; GFX12-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f32_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v0, v0, v4 :: v_dual_min_f32 v1, v1, v5
+; GFX11-REGBANK-NEXT: v_dual_min_f32 v2, v2, v6 :: v_dual_min_f32 v3, v3, v7
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f32_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v0, v0, v4 :: v_dual_min_num_f32 v1, v1, v5
+; GFX12-REGBANK-NEXT: v_dual_min_num_f32 v2, v2, v6 :: v_dual_min_num_f32 v3, v3, v7
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <4 x float> @llvm.minimumnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %result
}
@@ -8373,6 +9700,34 @@ define <2 x double> @v_minimumnum_v2f64(<2 x double> %x, <2 x double> %y) {
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f64:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-REGBANK-NEXT: v_max_f64 v[6:7], v[6:7], v[6:7]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-REGBANK-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f64:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> %y)
ret <2 x double> %result
}
@@ -8430,6 +9785,24 @@ define <2 x double> @v_minimumnum_v2f64_nnan(<2 x double> %x, <2 x double> %y) {
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f64_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[4:5]
+; GFX11-REGBANK-NEXT: v_min_f64 v[2:3], v[2:3], v[6:7]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f64_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[4:5]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[6:7]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> %y)
ret <2 x double> %result
}
@@ -8672,6 +10045,40 @@ define <3 x double> @v_minimumnum_v3f64(<3 x double> %x, <3 x double> %y) {
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f64:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[6:7], v[6:7], v[6:7]
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-REGBANK-NEXT: v_max_f64 v[8:9], v[8:9], v[8:9]
+; GFX11-REGBANK-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
+; GFX11-REGBANK-NEXT: v_max_f64 v[10:11], v[10:11], v[10:11]
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[6:7]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-REGBANK-NEXT: v_min_f64 v[2:3], v[2:3], v[8:9]
+; GFX11-REGBANK-NEXT: v_min_f64 v[4:5], v[4:5], v[10:11]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f64:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x double> @llvm.minimumnum.v3f64(<3 x double> %x, <3 x double> %y)
ret <3 x double> %result
}
@@ -8736,6 +10143,26 @@ define <3 x double> @v_minimumnum_v3f64_nnan(<3 x double> %x, <3 x double> %y) {
; GFX12-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f64_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[6:7]
+; GFX11-REGBANK-NEXT: v_min_f64 v[2:3], v[2:3], v[8:9]
+; GFX11-REGBANK-NEXT: v_min_f64 v[4:5], v[4:5], v[10:11]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f64_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[6:7]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[8:9]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[10:11]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <3 x double> @llvm.minimumnum.v3f64(<3 x double> %x, <3 x double> %y)
ret <3 x double> %result
}
@@ -9026,6 +10453,46 @@ define <4 x double> @v_minimumnum_v4f64(<4 x double> %x, <4 x double> %y) {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f64:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
+; GFX11-REGBANK-NEXT: v_max_f64 v[8:9], v[8:9], v[8:9]
+; GFX11-REGBANK-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3]
+; GFX11-REGBANK-NEXT: v_max_f64 v[10:11], v[10:11], v[10:11]
+; GFX11-REGBANK-NEXT: v_max_f64 v[4:5], v[4:5], v[4:5]
+; GFX11-REGBANK-NEXT: v_max_f64 v[12:13], v[12:13], v[12:13]
+; GFX11-REGBANK-NEXT: v_max_f64 v[6:7], v[6:7], v[6:7]
+; GFX11-REGBANK-NEXT: v_max_f64 v[14:15], v[14:15], v[14:15]
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[8:9]
+; GFX11-REGBANK-NEXT: v_min_f64 v[2:3], v[2:3], v[10:11]
+; GFX11-REGBANK-NEXT: v_min_f64 v[4:5], v[4:5], v[12:13]
+; GFX11-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-REGBANK-NEXT: v_min_f64 v[6:7], v[6:7], v[14:15]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f64:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[8:9], v[8:9], v[8:9]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[10:11], v[10:11], v[10:11]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[4:5], v[4:5], v[4:5]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[12:13], v[12:13], v[12:13]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[6:7], v[6:7], v[6:7]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[14:15], v[14:15], v[14:15]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[10:11]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> %x, <4 x double> %y)
ret <4 x double> %result
}
@@ -9097,6 +10564,28 @@ define <4 x double> @v_minimumnum_v4f64_nnan(<4 x double> %x, <4 x double> %y) {
; GFX12-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
; GFX12-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f64_nnan:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[8:9]
+; GFX11-REGBANK-NEXT: v_min_f64 v[2:3], v[2:3], v[10:11]
+; GFX11-REGBANK-NEXT: v_min_f64 v[4:5], v[4:5], v[12:13]
+; GFX11-REGBANK-NEXT: v_min_f64 v[6:7], v[6:7], v[14:15]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f64_nnan:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[8:9]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[2:3], v[2:3], v[10:11]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[4:5], v[4:5], v[12:13]
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[6:7], v[6:7], v[14:15]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <4 x double> @llvm.minimumnum.v4f64(<4 x double> %x, <4 x double> %y)
ret <4 x double> %result
}
@@ -9237,6 +10726,44 @@ define half @v_minimumnum_f16_no_ieee(half %x, half %y) #0 {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_no_ieee:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_no_ieee:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_no_ieee:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_no_ieee:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -9321,6 +10848,38 @@ define half @v_minimumnum_f16_nan_no_ieee(half %x, half %y) #0 {
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_nan_no_ieee:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_nan_no_ieee:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_nan_no_ieee:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_nan_no_ieee:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -9395,6 +10954,24 @@ define float @v_minimumnum_f32_no_ieee(float %x, float %y) #0 {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -9445,6 +11022,22 @@ define float @v_minimumnum_f32_nnan_no_ieee(float %x, float %y) #0 {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f32_nnan_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f32_nnan_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan float @llvm.minimumnum.f32(float %x, float %y)
ret float %result
}
@@ -9523,6 +11116,25 @@ define double @v_minimumnum_f64_no_ieee(double %x, double %y) #0 {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
+; GFX12-REGBANK-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3]
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -9573,6 +11185,22 @@ define double @v_minimumnum_f64_nnan_no_ieee(double %x, double %y) #0 {
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_f64_nnan_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_f64_nnan_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan double @llvm.minimumnum.f64(double %x, double %y)
ret double %result
}
@@ -9689,6 +11317,25 @@ define <2 x half> @v_minimumnum_v2f16_no_ieee(<2 x half> %x, <2 x half> %y) #0 {
; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-GISEL-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f16_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f16_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-REGBANK-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -9777,6 +11424,22 @@ define <2 x half> @v_minimumnum_v2f16_nnan_no_ieee(<2 x half> %x, <2 x half> %y)
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v2f16_nnan_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v1
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v2f16_nnan_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <2 x half> @llvm.minimumnum.v2f16(<2 x half> %x, <2 x half> %y)
ret <2 x half> %result
}
@@ -9887,6 +11550,24 @@ define <3 x half> @v_minimumnum_v3f16_nnan_no_ieee(<3 x half> %x, <3 x half> %y)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v3f16_nnan_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v3f16_nnan_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <3 x half> @llvm.minimumnum.v3f16(<3 x half> %x, <3 x half> %y)
ret <3 x half> %result
}
@@ -10010,6 +11691,24 @@ define <4 x half> @v_minimumnum_v4f16_nnan_no_ieee(<4 x half> %x, <4 x half> %y)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-REGBANK-LABEL: v_minimumnum_v4f16_nnan_no_ieee:
+; GFX11-REGBANK: ; %bb.0:
+; GFX11-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v0, v0, v2
+; GFX11-REGBANK-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX11-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-REGBANK-LABEL: v_minimumnum_v4f16_nnan_no_ieee:
+; GFX12-REGBANK: ; %bb.0:
+; GFX12-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v0, v0, v2
+; GFX12-REGBANK-NEXT: v_pk_min_num_f16 v1, v1, v3
+; GFX12-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan <4 x half> @llvm.minimumnum.v4f16(<4 x half> %x, <4 x half> %y)
ret <4 x half> %result
}
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