[llvm] [AMDGPU] Add legalizer rule support for AMDGPU's regbank fminimumnum and fmaximumnum (PR #192719)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 12:15:19 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jasmine Tang (badumbatish)
<details>
<summary>Changes</summary>
---
Patch is 118.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/192719.diff
3 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+10)
- (added) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir (+364)
- (modified) llvm/test/CodeGen/AMDGPU/minimumnum.ll (+1699)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index d84640c682ad8..5131f5d111d79 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1446,6 +1446,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
+ addRulesForGOpcs({G_FMINIMUMNUM, G_FMAXIMUMNUM}, Standard)
+ .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}})
+ .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
+ .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64}})
+ .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}});
+
addRulesForGOpcs({G_FPTRUNC})
.Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
.Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir
new file mode 100644
index 0000000000000..03ff508bbe8a6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fminimumnum.mir
@@ -0,0 +1,364 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -allow-unused-prefixes -check-prefixes=CHECK,GFX8 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -allow-unused-prefixes -check-prefixes=CHECK,GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -allow-unused-prefixes -check-prefixes=CHECK,GFX12 %s
+
+---
+name: fminimumnum_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fminimumnum_s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMINIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMINIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fminimumnum_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fminimumnum_s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMINIMUMNUM [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMINIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMINIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fminimumnum_s32_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fminimumnum_s32_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fminimumnum_s32_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fminimumnum_s32_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fminimumnum_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-LABEL: name: fminimumnum_s64_s
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUMNUM]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = COPY $sgpr2_sgpr3
+ %2:_(s64) = G_FMINIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fminimumnum_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-LABEL: name: fminimumnum_s64_v
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMINIMUMNUM]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_FMINIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fmaximumnum_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMAXIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMAXIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fmaximumnum_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s16) = G_FMAXIMUMNUM [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FMAXIMUMNUM]](s16)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_FMAXIMUMNUM %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: fmaximumnum_s32_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s32_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](s32)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $sgpr1
+ %2:_(s32) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_s32_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fmaximumnum_s32_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s32) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-LABEL: name: fmaximumnum_s64_s
+ ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUMNUM]](s64)
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = COPY $sgpr2_sgpr3
+ %2:_(s64) = G_FMAXIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fmaximumnum_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-LABEL: name: fmaximumnum_s64_v
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(s64) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FMAXIMUMNUM]](s64)
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(s64) = G_FMAXIMUMNUM %0, %1
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: fminimumnum_v2s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fminimumnum_v2s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMINIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $sgpr0
+ %1:_(<2 x s16>) = COPY $sgpr1
+ %2:_(<2 x s16>) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fminimumnum_v2s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fminimumnum_v2s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMINIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMINIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMINIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = COPY $vgpr1
+ %2:_(<2 x s16>) = G_FMINIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_v2s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; CHECK-LABEL: name: fmaximumnum_v2s16_s
+ ; CHECK: liveins: $sgpr0, $sgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMAXIMUMNUM [[COPY2]], [[COPY3]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $sgpr0
+ %1:_(<2 x s16>) = COPY $sgpr1
+ %2:_(<2 x s16>) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fmaximumnum_v2s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: fmaximumnum_v2s16_v
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; CHECK-NEXT: [[FMAXIMUMNUM:%[0-9]+]]:vgpr(<2 x s16>) = G_FMAXIMUMNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[FMAXIMUMNUM]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = COPY $vgpr1
+ %2:_(<2 x s16>) = G_FMAXIMUMNUM %0, %1
+ $vgpr0 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
index 87f76bab79ed0..c957fffed7d56 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.ll
@@ -32,6 +32,12 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-SDAG,GFX12-FAKE16-SDAG %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16,GFX12-GISEL,GFX12-FAKE16-GISEL %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-REGBANK,GFX11-FAKE16-REGBANK %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-REGBANK,GFX11-TRUE16-REGBANK %s
+
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-REGBANK,GFX12-FAKE16-REGBANK %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-REGBANK,GFX12-TRUE16-REGBANK %s
+
define half @v_minimumnum_f16(half %x, half %y) {
; GFX7-SDAG-LABEL: v_minimumnum_f16:
; GFX7-SDAG: ; %bb.0:
@@ -222,6 +228,50 @@ define half @v_minimumnum_f16(half %x, half %y) {
; GFX12-FAKE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-GISEL-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v0, v0, v0
+; GFX11-FAKE16-REGBANK-NEXT: v_max_f16_e32 v1, v1, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-REGBANK-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v0, v0, v0
+; GFX12-FAKE16-REGBANK-NEXT: v_max_num_f16_e32 v1, v1, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
+; GFX12-TRUE16-REGBANK-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -306,6 +356,38 @@ define half @v_minimumnum_f16_nnan(half %x, half %y) {
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX11-FAKE16-REGBANK: ; %bb.0:
+; GFX11-FAKE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-REGBANK-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX11-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX11-TRUE16-REGBANK: ; %bb.0:
+; GFX11-TRUE16-REGBANK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-REGBANK-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX12-FAKE16-REGBANK: ; %bb.0:
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-REGBANK-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-REGBANK-LABEL: v_minimumnum_f16_nnan:
+; GFX12-TRUE16-REGBANK: ; %bb.0:
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-REGBANK-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-REGBANK-NEXT: s_setpc_b64 s[30:31]
%result = call nnan half @llvm.minimumnum.f16(half %x, half %y)
ret half %result
}
@@ -395,6 +477,46 @@ define half @v_minimumnum_f16_1.0(half %x) {
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, 1.0, v0
; GFX12-FAKE16-NEXT: s_setpc...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/192719
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