[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

sushgokh wrote:

> Hi, this seems like a more general combine for (and sext (i1), splat (1)). Any reason to make this specific to AArch64ISD::SETCC_MERGE_ZERO?

@rj-jesus  I need to recorrect myself. The earliest thing I  see is 
```
       t20: v32i8 = setcc t9, t10, setlt:ch
        t24: v32i8 = splat_vector Constant:i32<1>
      t23: v32i8 = and t20, t24
```
I cant fold here because setcc type has change from 32i1 to 32i8.

After that, what I see is `AArch64ISD::SETCC_MERGE_ZERO` and hence I would need to use this code

https://github.com/llvm/llvm-project/pull/192405