[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

Does it matter that the op inside the sign-extension is specifically AArch64ISD::SETCC_MERGE_ZERO? I think you only need the element type of the inner op to be i1?

https://github.com/llvm/llvm-project/pull/192405