[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Ricardo Jesus via llvm-commits]

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@@ -0,0 +1,138 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 --aarch64-sve-vector-bits-min=256 -o - < %s | FileCheck %s
+
+define <vscale x 16 x i8> @zext_slt_test1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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rj-jesus wrote:

The type doesn't matter, but it matters that the correct type is used. With the patch as is, you could do:
```
return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::nxv16i8, Compare);
```
And I believe no test would catch the error.

https://github.com/llvm/llvm-project/pull/192405