[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

================
@@ -0,0 +1,138 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 --aarch64-sve-vector-bits-min=256 -o - < %s | FileCheck %s
+
+define <vscale x 16 x i8> @zext_slt_test1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
----------------
sushgokh wrote:

> It remains relevant even then because you'll still what to verify the result type matches expectation. At the end of the day we're only talking about one more test, perhaps not even that if the result type variation is done alongside another variation.

So, just to reiterate, this patch is affecting the output where I am inserting the `zext` output into the scalable vector. 

At the early stages of SDAG, where the output looks like
```
t20: v32i8 = setcc t9, t10, setlt:ch
        t24: v32i8 = splat_vector Constant:i32<1>
      t23: v32i8 = and t20, t24
    t16: nxv16i8 = insert_subvector poison:nxv16i8, t23, Constant:i64<0>
```
, the insert_vector type or the result type doesnt even matter because I would be intercepting at the `and` instruction.

So, do you still think I should add cases with different result types e.g. zext_slt_nxv2i64 ?

https://github.com/llvm/llvm-project/pull/192405