[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

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@@ -0,0 +1,138 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 --aarch64-sve-vector-bits-min=256 -o - < %s | FileCheck %s
+
+define <vscale x 16 x i8> @zext_slt_test1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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sushgokh wrote:

> Could you please rename the tests based on the types used (e.g. `zext_slt_test1` --> `zext_slt_nxv16i8`) and move the curly brace to the same line as the signature?

Sure, will make the changes. 

> Can you also add a few tests for sext(icmp), other condition codes, and other element types? (I don't mean full coverage for all combinations of these, but it's worth having some combinations tested.)

I am planning to keep the scope limited to `zext` for this patch. For `sext`, I will add patterns in #192052. Does this sound good ?

https://github.com/llvm/llvm-project/pull/192405