[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Ricardo Jesus via llvm-commits]

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@@ -20942,12 +20942,30 @@ static SDValue performReinterpretCastCombine(SDNode *N) {
   return SDValue();
 }
 
+// and(splat(1), sext(setcc_merge_zero)) -> zext(setcc_merge_zero)
+SDValue performSVEAndSplatSetCCMergeZeroCombine(SDNode *N, SelectionDAG &DAG) {
+  SDLoc DL(N);
+  SDValue SplatOp = N->getOperand(0);
+  SDValue NonSplatOp = N->getOperand(1);
+  if (NonSplatOp.getOpcode() == ISD::SPLAT_VECTOR)
+    std::swap(SplatOp, NonSplatOp);
+  SDValue Compare = NonSplatOp.getOperand(0);
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rj-jesus wrote:

Ensure that NonSplatOp is a sign-extend before accessing the operand.

https://github.com/llvm/llvm-project/pull/192405