[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

sushgokh wrote:

> Hi, this seems like a more general combine for (and sext (i1), splat (1)). Any reason to make this specific to AArch64ISD::SETCC_MERGE_ZERO?

Missed through this pattern at the initial stages. Will make changes

https://github.com/llvm/llvm-project/pull/192405