[llvm] [AMDGPU] Analyze implicit reg operands when generating swaps (PR #192220)

[Juan Manuel Martinez Caamaño via llvm-commits]

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@@ -639,14 +636,25 @@ bool SIShrinkInstructions::instAccessReg(
   return false;
 }
 
-bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, unsigned Reg,
-                                        unsigned SubReg) const {
-  return instAccessReg(MI->uses(), Reg, SubReg);
-}
-
-bool SIShrinkInstructions::instModifiesReg(const MachineInstr *MI, unsigned Reg,
+// This is the same as MachineInstr::modifiesRegister except
+// it takes subregs into account.
+bool SIShrinkInstructions::instModifiesReg(const MachineInstr *MI, Register Reg,
                                            unsigned SubReg) const {
-  return instAccessReg(MI->defs(), Reg, SubReg);
+  for (const MachineOperand &MO : MI->all_defs()) {
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jmmartinez wrote:

Nice catch. The change is very subtle. `defs()` is actually `explicit defs` and `all_defs` is explicit and implicit.

https://github.com/llvm/llvm-project/pull/192220