[llvm] [AMDGPU] Analyze implicit reg operands when generating swaps (PR #192220)

[Juan Manuel Martinez Caamaño via llvm-commits]

================
@@ -617,12 +615,11 @@ ChangeKind SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
   return ChangeKind::None;
 }
 
-// This is the same as MachineInstr::readsRegister/modifiesRegister except
+// This is the same as MachineInstr::readsRegister except
 // it takes subregs into account.
-bool SIShrinkInstructions::instAccessReg(
-    iterator_range<MachineInstr::const_mop_iterator> &&R, Register Reg,
-    unsigned SubReg) const {
-  for (const MachineOperand &MO : R) {
+bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, Register Reg,
+                                        unsigned SubReg) const {
+  for (const MachineOperand &MO : MI->all_uses()) {
     if (!MO.isReg())
       continue;
----------------
jmmartinez wrote:

You can avoid this now right? 

`all_uses()` is the same as `uses()` filtered by

```cpp
  static bool opIsRegUse(const MachineOperand &Op) {
    return Op.isReg() && Op.isUse();
  }
```
---

The same happens for `all_defs()`

https://github.com/llvm/llvm-project/pull/192220