[llvm] [AMDGPU] Analyze implicit reg operands when generating swaps (PR #192220)

[Juan Manuel Martinez Caamaño via llvm-commits]

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@@ -617,12 +615,11 @@ ChangeKind SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
   return ChangeKind::None;
 }
 
-// This is the same as MachineInstr::readsRegister/modifiesRegister except
+// This is the same as MachineInstr::readsRegister except
 // it takes subregs into account.
-bool SIShrinkInstructions::instAccessReg(
-    iterator_range<MachineInstr::const_mop_iterator> &&R, Register Reg,
-    unsigned SubReg) const {
-  for (const MachineOperand &MO : R) {
+bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, Register Reg,
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jmmartinez wrote:

I find the code duplication not great though.

What do you think about bringing back `instAccessReg` but making the input argument a template or a `filtered_const_mop_range` (both, all_uses and all_defs are).

https://github.com/llvm/llvm-project/pull/192220