[llvm] [RISCV] Support MachineOutlinerRegSave for RISCV (PR #191351)

[Piyou Chen via llvm-commits]

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@@ -3714,7 +3748,16 @@ bool RISCVInstrInfo::analyzeCandidate(outliner::Candidate &C) const {
       }))
     return true;
 
-  return !C.isAvailableAcrossAndOutOfSeq(RISCV::X5, RegInfo);
+  bool X5Available = C.isAvailableAcrossAndOutOfSeq(RISCV::X5, RegInfo);
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BeMg wrote:

I think we only need x5 for the jump to the outlined function. If x5 is available, just use it (MachineOutlinerDefault). Otherwise, check the other temporary registers (t1-6) to preserve the original value of x5.(MachineOutlinerRegSave)

Added the comment.

https://github.com/llvm/llvm-project/pull/191351