[llvm] [RISCV] Support MachineOutlinerRegSave for RISCV (PR #191351)

[Piyou Chen via llvm-commits]

================
@@ -3714,7 +3748,16 @@ bool RISCVInstrInfo::analyzeCandidate(outliner::Candidate &C) const {
       }))
     return true;
----------------
BeMg wrote:

I think it should be more like:

```
    if (C.isAvailableAcrossAndOutOfSeq(Reg, TRI) &&
        C.isAvailableInsideSeq(Reg, TRI)) {
```

If drop the llvm::any_of check, `llvm/test/CodeGen/RISCV/machine-outliner-call-reg-live-across.mir` will fail because the one outlined function modifies X5. This behavior is not expected.

https://github.com/llvm/llvm-project/pull/191351