[llvm] [RISCV] Support MachineOutlinerRegSave for RISCV (PR #191351)

[Piyou Chen via llvm-commits]

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@@ -3779,8 +3822,26 @@ RISCVInstrInfo::getOutliningCandidateInfo(
   if (MOCI != MachineOutlinerTailCall && CFICount > 0)
     return std::nullopt;
 
-  for (auto &C : RepeatedSequenceLocs)
-    C.setCallInfo(MOCI, CallOverhead);
+  if (OutlinerEnableRegSave && MOCI == MachineOutlinerDefault) {
+    // Set per-candidate overhead based on X5 availability
+    for (auto &C : RepeatedSequenceLocs) {
+      unsigned CandCallOverhead;
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BeMg wrote:

Move unsigned CandCallOverhead to use 

https://github.com/llvm/llvm-project/pull/191351