[llvm] [AMDGPU] Fix setreg handling in the VGPR MSB lowering (PR #186491)

[Shilei Tian via llvm-commits]

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@@ -485,57 +484,43 @@ bool AMDGPULowerVGPREncoding::handleSetregMode(MachineInstr &MI) {
            << " VGPRMSBShift=" << VGPRMSBShift << '\n';
   });
 
-  // Case 1: Size <= 12 - the original instruction uses imm32[0:Size-1], so
-  // imm32[12:19] is unused. Safe to set imm32[12:19] to the correct VGPR
-  // MSBs.
-  if (Size <= VGPRMSBShift) {
+  // Case 1: immediate has mode bits, we can update it.
+  if (Offset <= VGPRMSBShift) {
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shiltian wrote:

I refreshed my memory a bit, and I remember why `Offset` is completely ignored here. It is not because we assume `Offset` has to be zero here. IIRC, instead, `Offset` is only used to control which bits in the MODE register the write starts from, and `Size` controls how many bits are written. The `Imm32` only contains the bits to be written, without considering the offset.

For example, if we want to write to `Bits[19:12]`, then `Offset` is 12 and `Size` is 8. `Imm32[7:0]` will be written into `Bits[19:12]`. That's why `Offset` doesn't really matter here, because `Imm32[19:12]` would still overwrite `Bits[19:12]`.

https://github.com/llvm/llvm-project/pull/186491