[llvm] [AMDGPU] Fix setreg handling in the VGPR MSB lowering (PR #186491)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -485,57 +484,43 @@ bool AMDGPULowerVGPREncoding::handleSetregMode(MachineInstr &MI) {
            << " VGPRMSBShift=" << VGPRMSBShift << '\n';
   });
 
-  // Case 1: Size <= 12 - the original instruction uses imm32[0:Size-1], so
-  // imm32[12:19] is unused. Safe to set imm32[12:19] to the correct VGPR
-  // MSBs.
-  if (Size <= VGPRMSBShift) {
+  // Case 1: immediate has mode bits, we can update it.
+  if (Offset <= VGPRMSBShift) {
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rampitec wrote:

And then, Offset is the first covered bit. It shall just not exclude any of the MSBs.

https://github.com/llvm/llvm-project/pull/186491