[llvm] [AMDGPU] Fix incorrect VGPR usage for `s` constrained inline asm (PR #184910)

[Chinmay Deshpande via llvm-commits]

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@@ -1019,6 +1019,17 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
 // The main function that computes the VGPR to SGPR copy score
 // and determines copy further lowering way: v_readfirstlane_b32 or moveToVALU
 bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
+  Register DstReg = Info->Copy->getOperand(0).getReg();
+  for (const MachineOperand &MO : MRI->use_nodbg_operands(DstReg)) {
+    const MachineInstr *UseMI = MO.getParent();
+    if (!UseMI->isInlineAsm())
+      continue;
+    const TargetRegisterClass *RC =
+        UseMI->getRegClassConstraint(MO.getOperandNo(), TII, TRI);
+    if (RC && TRI->isSGPRClass(RC))
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chinmaydd wrote:

Correct me if wrong, but there's some contradiction in the two questions. We effectively want to check if any inline asm use of `DstReg` has an "s" constraint / `isSGPRClass`. If it is, then we return `false`.

So if the first use doesnt need to, but the second does we handle that.

> We just check the first use that doesn't need to, and then return false here

Yes. If NONE of the uses satisfy the conditional, only then we clear this case.

https://github.com/llvm/llvm-project/pull/184910