[llvm] [AMDGPU] Fix incorrect VGPR usage for `s` constrained inline asm (PR #184910)

[Shilei Tian via llvm-commits]

================
@@ -1019,6 +1019,17 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
 // The main function that computes the VGPR to SGPR copy score
 // and determines copy further lowering way: v_readfirstlane_b32 or moveToVALU
 bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
+  Register DstReg = Info->Copy->getOperand(0).getReg();
+  for (const MachineOperand &MO : MRI->use_nodbg_operands(DstReg)) {
+    const MachineInstr *UseMI = MO.getParent();
+    if (!UseMI->isInlineAsm())
+      continue;
+    const TargetRegisterClass *RC =
+        UseMI->getRegClassConstraint(MO.getOperandNo(), TII, TRI);
+    if (RC && TRI->isSGPRClass(RC))
----------------
shiltian wrote:

We just check the first use that doesn't need to, and then return false here? What if the 1st use doesn't need to but the 2nd does? Or that can't happen?

https://github.com/llvm/llvm-project/pull/184910