[llvm] [TableGen] Fix ordering of register classes with artificial members. (PR #185448)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tablegen

Author: Ivan Kosarev (kosarev)

<details>
<summary>Changes</summary>

The current implementation wouldn't advance IB to skip artificial registers once IA has reached the end.

---
Full diff: https://github.com/llvm/llvm-project/pull/185448.diff


1 Files Affected:

- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+8-10) 


``````````diff
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 98aa63b3adb2d..fcd85cea6ffac 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -851,23 +851,21 @@ bool CodeGenRegisterClass::Key::operator<(
   // artificial registers.
   auto IA = Members->begin(), EA = Members->end();
   auto IB = B.Members->begin(), EB = B.Members->end();
-  while (IA != EA && IB != EB) {
-    if ((*IA)->Artificial) {
+  for (;;) {
+    while (IA != EA && (*IA)->Artificial)
       ++IA;
-      continue;
-    }
-    if ((*IB)->Artificial) {
+    while (IB != EB && (*IB)->Artificial)
       ++IB;
-      continue;
-    }
+    if (IA == EA && IB == EB)
+      break;
+    if (IA == EA || IB == EB)
+      return IA == EA;
     if (*IA != *IB)
       return *IA < *IB;
     ++IA;
     ++IB;
   }
-  if (IA == EA && IB == EB)
-    return RSI < B.RSI;
-  return IA == EA;
+  return RSI < B.RSI;
 }
 
 // Returns true if RC is a strict subclass.

``````````

</details>


https://github.com/llvm/llvm-project/pull/185448