[llvm] [TableGen] Fix ordering of register classes with artificial members. (PR #185448)

[Ivan Kosarev via llvm-commits]

https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/185448

The current implementation wouldn't advance IB to skip artificial registers once IA has reached the end.

>From 6d3517b964a1c6ab9907d850bbfda56263abf362 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Mon, 9 Mar 2026 16:00:44 +0000
Subject: [PATCH] [TableGen] Fix ordering of register classes with artificial
 members.

The current implementation wouldn't advance IB to skip artificial
registers once IA has reached the end.
---
 .../utils/TableGen/Common/CodeGenRegisters.cpp | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 98aa63b3adb2d..fcd85cea6ffac 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -851,23 +851,21 @@ bool CodeGenRegisterClass::Key::operator<(
   // artificial registers.
   auto IA = Members->begin(), EA = Members->end();
   auto IB = B.Members->begin(), EB = B.Members->end();
-  while (IA != EA && IB != EB) {
-    if ((*IA)->Artificial) {
+  for (;;) {
+    while (IA != EA && (*IA)->Artificial)
       ++IA;
-      continue;
-    }
-    if ((*IB)->Artificial) {
+    while (IB != EB && (*IB)->Artificial)
       ++IB;
-      continue;
-    }
+    if (IA == EA && IB == EB)
+      break;
+    if (IA == EA || IB == EB)
+      return IA == EA;
     if (*IA != *IB)
       return *IA < *IB;
     ++IA;
     ++IB;
   }
-  if (IA == EA && IB == EB)
-    return RSI < B.RSI;
-  return IA == EA;
+  return RSI < B.RSI;
 }
 
 // Returns true if RC is a strict subclass.