[llvm] Allow the nolds modifier (PR #185129)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 6 15:11:46 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jun Wang (jwanggit86)
<details>
<summary>Changes</summary>
Some pre-GFX11 buffer_load instructions have two variants: one
requires the lds modifier and one does not allow lds. For the latter
allow nolds to be used.
---
Patch is 403.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/185129.diff
9 Files Affected:
- (added) llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst (+1620)
- (added) llvm/docs/AMDGPU/gfx950_operands.rst (+1495)
- (modified) llvm/docs/AMDGPUUsage.rst (+3)
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+1)
- (modified) llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s (+18)
- (modified) llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s (+18)
- (modified) llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s (+18)
- (modified) llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s (+18)
``````````diff
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
new file mode 100644
index 0000000000000..175f82af5596e
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
@@ -0,0 +1,1620 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+====================================================================================
+Syntax of GFX950 Instructions
+====================================================================================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+This document describes the syntax of GFX950 instructions.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+--
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b128 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/185129
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