[llvm] Allow the nolds modifier (PR #185129)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 6 15:11:26 PST 2026
https://github.com/jwanggit86 created https://github.com/llvm/llvm-project/pull/185129
Some pre-GFX11 buffer_load instructions have two variants: one
requires the lds modifier and one does not allow lds. For the latter
allow nolds to be used.
>From 5485ceb13d1e92008f398131580b0ae6f423dcd2 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Wed, 4 Mar 2026 16:19:12 -0800
Subject: [PATCH 1/3] [AMDGPU] Documentation files for GFX950 instructions
Checking in documentation files for GFX950 instructions.
---
llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst | 1749 ++++++++++++++++++++
llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst | 15 +
llvm/docs/AMDGPU/gfx950_addr_f2b449.rst | 15 +
llvm/docs/AMDGPU/gfx950_attr.rst | 29 +
llvm/docs/AMDGPU/gfx950_data0_848ff7.rst | 17 +
llvm/docs/AMDGPU/gfx950_data0_9ad749.rst | 17 +
llvm/docs/AMDGPU/gfx950_data0_be4895.rst | 17 +
llvm/docs/AMDGPU/gfx950_data0_cfb402.rst | 17 +
llvm/docs/AMDGPU/gfx950_data1_9ad749.rst | 17 +
llvm/docs/AMDGPU/gfx950_data1_be4895.rst | 17 +
llvm/docs/AMDGPU/gfx950_data_848ff7.rst | 17 +
llvm/docs/AMDGPU/gfx950_data_9ad749.rst | 17 +
llvm/docs/AMDGPU/gfx950_data_be4895.rst | 17 +
llvm/docs/AMDGPU/gfx950_data_cfb402.rst | 17 +
llvm/docs/AMDGPU/gfx950_literal_39b593.rst | 15 +
llvm/docs/AMDGPU/gfx950_literal_81e671.rst | 15 +
llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst | 15 +
llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst | 15 +
llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst | 17 +
llvm/docs/AMDGPU/gfx950_sbase_044055.rst | 17 +
llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst | 17 +
llvm/docs/AMDGPU/gfx950_scale_src0.rst | 17 +
llvm/docs/AMDGPU/gfx950_scale_src1.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_362c37.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_94342d.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst | 21 +
llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst | 21 +
llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst | 21 +
llvm/docs/AMDGPU/gfx950_sdst_02b357.rst | 15 +
llvm/docs/AMDGPU/gfx950_sdst_06b266.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdst_1db612.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdst_94342d.rst | 17 +
llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst | 17 +
llvm/docs/AMDGPU/gfx950_simm16_218bea.rst | 15 +
llvm/docs/AMDGPU/gfx950_simm16_39b593.rst | 15 +
llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst | 15 +
llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst | 15 +
llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst | 17 +
llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst | 15 +
llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst | 20 +
llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst | 17 +
llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_06ee74.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_0f0007.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_1027ca.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_14b47a.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_168f33.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_1d4114.rst | 13 +
llvm/docs/AMDGPU/gfx950_src0_516946.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_6802ce.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_848ff7.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_9ad749.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_be4895.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_ca334d.rst | 17 +
llvm/docs/AMDGPU/gfx950_src0_e30a18.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_14b47a.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_43aa79.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_6802ce.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_848ff7.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_9ad749.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_be4895.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_ca334d.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_d52854.rst | 17 +
llvm/docs/AMDGPU/gfx950_src1_e30a18.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_14b47a.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_1ff383.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_581e7b.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_6802ce.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_e016a1.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_e30a18.rst | 17 +
llvm/docs/AMDGPU/gfx950_src2_f36021.rst | 17 +
llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst | 17 +
llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssamp.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst | 17 +
llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst | 17 +
llvm/docs/AMDGPU/gfx950_tgt.rst | 23 +
llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst | 21 +
llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst | 22 +
llvm/docs/AMDGPU/gfx950_vcc.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdata_180bef.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdata_260aca.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst | 26 +
llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst | 21 +
llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst | 21 +
llvm/docs/AMDGPU/gfx950_vdata_576598.rst | 26 +
llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst | 21 +
llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst | 20 +
llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst | 20 +
llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_180bef.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_260aca.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_363335.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_59204c.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_69a144.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_89680f.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst | 19 +
llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst | 17 +
llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst | 19 +
llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst | 17 +
llvm/docs/AMDGPU/gfx950_vsrc.rst | 21 +
llvm/docs/AMDGPU/gfx950_vsrc0.rst | 17 +
llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst | 17 +
llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst | 17 +
llvm/docs/AMDGPU/gfx950_vsrc2.rst | 17 +
llvm/docs/AMDGPU/gfx950_vsrc3.rst | 17 +
llvm/docs/AMDGPUUsage.rst | 3 +
132 files changed, 4020 insertions(+)
create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_addr_f2b449.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_attr.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data0_848ff7.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data0_9ad749.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data0_be4895.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data0_cfb402.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data1_9ad749.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data1_be4895.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data_848ff7.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data_9ad749.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data_be4895.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_data_cfb402.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_literal_39b593.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_literal_81e671.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sbase_044055.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_scale_src0.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_scale_src1.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_362c37.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_94342d.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_02b357.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_06b266.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_1db612.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_94342d.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_simm16_218bea.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_simm16_39b593.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_06ee74.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_0f0007.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_1027ca.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_14b47a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_168f33.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_1d4114.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_516946.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_6802ce.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_848ff7.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_9ad749.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_be4895.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_ca334d.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src0_e30a18.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_14b47a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_43aa79.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_6802ce.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_848ff7.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_9ad749.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_be4895.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_ca334d.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_d52854.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src1_e30a18.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_14b47a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_1ff383.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_581e7b.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_6802ce.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_e016a1.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_e30a18.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_src2_f36021.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssamp.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_tgt.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vcc.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_180bef.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_260aca.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_576598.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_180bef.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_260aca.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_363335.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_59204c.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_69a144.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_89680f.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vsrc.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vsrc0.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vsrc2.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_vsrc3.rst
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
new file mode 100644
index 0000000000000..f5f1ece2ffaff
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
@@ -0,0 +1,1749 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+====================================================================================
+Syntax of GFX950 Instructions
+====================================================================================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+This document describes the syntax of GFX950 instructions.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DS
+--
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b128 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_bf16 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_f16 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_rtn_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_pk_add_rtn_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64_tr_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64_tr_b4 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64_tr_b8 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid_gfx950_vdst_260aca>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96_tr_b6 :ref:`vdst<amdgpu_synid_gfx950_vdst_260aca>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_addtid_b32 :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_848ff7>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_cfb402>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>`, :ref:`data1<amdgpu_synid_gfx950_data1_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>`, :ref:`data1<amdgpu_synid_gfx950_data1_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_be4895>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data0<amdgpu_synid_gfx950_data0_9ad749>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+---
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ exp :ref:`tgt<amdgpu_synid_gfx950_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx950_vsrc0>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vsrc2<amdgpu_synid_gfx950_vsrc2>`, :ref:`vsrc3<amdgpu_synid_gfx950_vsrc3>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_add_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_848ff7>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_max_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_min_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_pk_add_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx950_vdst_c8ee02>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_ef6c94>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_dword :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx950_vdst_260aca>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_byte :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_byte_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_dword :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_dwordx2 :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_dwordx3 :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_cfb402>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_dwordx4 :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_848ff7>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_short :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ flat_store_short_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+
+FLAT_GLBL
+---------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_add_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_848ff7>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_max_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_min_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_pk_add_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_dword :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx950_vdst_260aca>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_dword :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_dwordx2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_dwordx3 :ref:`vdst<amdgpu_synid_gfx950_vdst_260aca>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_dwordx4 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_sbyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_sshort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_ubyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_lds_ushort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_sshort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_load_ushort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_byte :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_byte_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_dword :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_dwordx2 :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_dwordx3 :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_cfb402>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_dwordx4 :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_848ff7>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_short :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+ global_store_short_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_f2b449>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_ce8216>`
+
+FLAT_SCRATCH
+------------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ scratch_load_dword :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx950_vdst_260aca>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_lds_dword :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_lds_sbyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_lds_sshort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_lds_ubyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_lds_ushort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_byte :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_byte_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_dword :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_dwordx2 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_9ad749>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_dwordx3 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_cfb402>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_dwordx4 :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_848ff7>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_short :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+ scratch_store_short_d16_hi :ref:`addr<amdgpu_synid_gfx950_addr_c8b8d4>`, :ref:`data<amdgpu_synid_gfx950_data_be4895>`, :ref:`saddr<amdgpu_synid_gfx950_saddr_13d69a>`
+
+MIMG
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx950_vdata_576598>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx950_vdata_2a143d>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4 :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_b_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_b_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_l :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_l_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_lz :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_lz_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_c_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_l :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_l_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_lz :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_lz_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4h :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather4h_pck :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_gather8h_pck :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_get_lod :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_get_resinfo :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_load :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_load_mip :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_load_mip_pck :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_load_mip_pck_sgn :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_load_pck :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_load_pck_sgn :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_rsrc256 :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_b_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_b_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cd :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cd_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cd_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cd_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_d :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_d_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_d_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_d_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_l :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_l_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_lz :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_lz_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_c_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cd :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cd_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cd_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cd_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cl_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_cl_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_d :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_d_cl :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_d_cl_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_d_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_l :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_l_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_lz :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_lz_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_o :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sample_o_a :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>`, :ref:`ssamp<amdgpu_synid_gfx950_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_sampler :ref:`vdata<amdgpu_synid_gfx950_vdata_a507a0>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_store :ref:`vdata<amdgpu_synid_gfx950_vdata_a5f23e>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_store_mip :ref:`vdata<amdgpu_synid_gfx950_vdata_a5f23e>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx950_vdata_a5f23e>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ image_store_pck :ref:`vdata<amdgpu_synid_gfx950_vdata_a5f23e>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_5d0b42>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_79ffcd>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+
+MTBUF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ tbuffer_load_format_d16_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_d16_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_260aca>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_load_format_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_180bef>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_260aca>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_180bef>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`fmt<amdgpu_synid_fmt>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+
+MUBUF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_add_f32 :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_add_f64 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_8e9b87>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_max_f64 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_min_f64 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_pk_add_bf16 :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_pk_add_f16 :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx950_vdata_2a60db>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx950_vdata_2d0375>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_inv :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_dword :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_dwordx2 :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_dwordx3 :ref:`vdata<amdgpu_synid_gfx950_vdata_260aca>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_dwordx4 :ref:`vdata<amdgpu_synid_gfx950_vdata_180bef>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_d16_hi_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_d16_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_d16_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_260aca>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_format_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_180bef>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_sbyte :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_sbyte_d16 :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_sbyte_d16_hi :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_short_d16 :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_short_d16_hi :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_sshort :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_ubyte :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_ubyte_d16 :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_ubyte_d16_hi :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_load_ushort :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx950_vdata_260aca>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx950_vdata_180bef>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_d16_hi_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx950_vdata_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx950_vdata_260aca>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx950_vdata_180bef>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_lds_dword :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_wbinvl1 :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_wbinvl1_vol :ref:`vdata<amdgpu_synid_gfx950_vdata_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx950_vaddr_7a736f>`, :ref:`srsrc<amdgpu_synid_gfx950_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_d856a0>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+ buffer_wbl2 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offen<amdgpu_synid_offen>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`lds<amdgpu_synid_lds>` :ref:`sc0<amdgpu_synid_sc0>` :ref:`sc1<amdgpu_synid_sc1>` :ref:`nt<amdgpu_synid_nt>`
+
+SMEM
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_atc_probe :ref:`sdata<amdgpu_synid_gfx950_sdata_d725ab>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atc_probe_buffer :ref:`sdata<amdgpu_synid_gfx950_sdata_d725ab>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_atomic_add :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_and :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_c6aec1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_dec :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_inc :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_or :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_smax :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_smin :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_sub :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_swap :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_umax :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_umin :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_xor :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_buffer_atomic_add :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_and :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_c6aec1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_dec :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_inc :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_or :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_smax :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_smin :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_sub :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_swap :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_umax :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_umin :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_xor :ref:`sdata<amdgpu_synid_gfx950_sdata_aefe00>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid_gfx950_sdata_eb6f2a>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_load_dword :ref:`sdata<amdgpu_synid_gfx950_sdata_94342d>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_load_dwordx16 :ref:`sdata<amdgpu_synid_gfx950_sdata_3bc700>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_load_dwordx2 :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_load_dwordx4 :ref:`sdata<amdgpu_synid_gfx950_sdata_0804b1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_load_dwordx8 :ref:`sdata<amdgpu_synid_gfx950_sdata_362c37>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_store_dword :ref:`sdata<amdgpu_synid_gfx950_sdata_94342d>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx950_sdata_0804b1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_8aa27a>`
+ s_dcache_discard :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_dcache_discard_x2 :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_dcache_inv
+ s_dcache_inv_vol
+ s_dcache_wb
+ s_dcache_wb_vol
+ s_load_dword :ref:`sdata<amdgpu_synid_gfx950_sdata_94342d>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_load_dwordx16 :ref:`sdata<amdgpu_synid_gfx950_sdata_3bc700>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_load_dwordx2 :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_load_dwordx4 :ref:`sdata<amdgpu_synid_gfx950_sdata_0804b1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_load_dwordx8 :ref:`sdata<amdgpu_synid_gfx950_sdata_362c37>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_memrealtime :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`
+ s_memtime :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`
+ s_scratch_load_dword :ref:`sdata<amdgpu_synid_gfx950_sdata_94342d>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_scratch_load_dwordx2 :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_scratch_load_dwordx4 :ref:`sdata<amdgpu_synid_gfx950_sdata_0804b1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_scratch_store_dword :ref:`sdata<amdgpu_synid_gfx950_sdata_94342d>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx950_sdata_0804b1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_0cd545>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_store_dword :ref:`sdata<amdgpu_synid_gfx950_sdata_94342d>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_store_dwordx2 :ref:`sdata<amdgpu_synid_gfx950_sdata_718cc4>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+ s_store_dwordx4 :ref:`sdata<amdgpu_synid_gfx950_sdata_0804b1>`, :ref:`sbase<amdgpu_synid_gfx950_sbase_044055>`, :ref:`soffset<amdgpu_synid_gfx950_soffset_1189ef>`
+
+SOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_cbranch_join :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_595c25>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_mov_fed_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_mov_regrd_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_94342d>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_595c25>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_e9f591>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_not_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_not_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_rfe_b64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_e9f591>`
+ s_set_gpr_idx_idx :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_setpc_b64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_e9f591>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_e9f591>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_718cc4>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`
+
+SOP2
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_absdiff_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_add_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_add_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_and_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_and_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_1ce478>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_1ce478>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_max_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_max_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_min_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_min_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_or_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_or_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_rfe_restore_b64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+
+SOPC
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_83ef5a>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_83ef5a>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+ s_set_gpr_idx_on :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_5c7b50>`
+ s_setvskip :ref:`ssrc0<amdgpu_synid_gfx950_ssrc0_eecc17>`, :ref:`ssrc1<amdgpu_synid_gfx950_ssrc1_eecc17>`
+
+SOPK
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_i_fork :ref:`sdst<amdgpu_synid_gfx950_sdst_a319e6>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_eq_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_eq_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_ge_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_ge_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_gt_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_gt_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_le_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_le_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_lg_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_lg_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_lt_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_cmpk_lt_u32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_7ed651>`
+ s_getreg_regrd_b32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_7ed651>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx950_sdst_06b266>`, :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_setreg_b32 :ref:`simm16<amdgpu_synid_gfx950_simm16_cc1716>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_02b357>`
+ s_setreg_imm32_b32 :ref:`simm16<amdgpu_synid_gfx950_simm16_cc1716>`, :ref:`literal<amdgpu_synid_gfx950_literal_81e671>`
+
+SOPP
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_cdbgsys :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_cdbgsys_and_user :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_cdbgsys_or_user :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_cdbguser :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_execnz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_execz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_scc0 :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_scc1 :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_vccnz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_cbranch_vccz :ref:`simm16<amdgpu_synid_gfx950_simm16_3d2a4f>`
+ s_decperflevel :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_endpgm
+ s_endpgm_ordered_ps_done
+ s_endpgm_saved
+ s_icache_inv
+ s_incperflevel :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_nop :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_sendmsg :ref:`simm16<amdgpu_synid_gfx950_simm16_ee8b30>`
+ s_sendmsghalt :ref:`simm16<amdgpu_synid_gfx950_simm16_ee8b30>`
+ s_set_gpr_idx_mode :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_set_gpr_idx_off
+ s_set_valu_coexec_mode :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_sethalt :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_setkill :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_setprio :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_sleep :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_trap :ref:`simm16<amdgpu_synid_gfx950_simm16_39b593>`
+ s_ttracedata
+ s_waitcnt :ref:`simm16<amdgpu_synid_gfx950_simm16_218bea>`
+ s_wakeup
+
+VERIF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_illegal
+ s_nowaitcnt
+
+VINTRP
+------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx950_vsrc>`, :ref:`attr<amdgpu_synid_gfx950_attr>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx950_vsrc>`, :ref:`attr<amdgpu_synid_gfx950_attr>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx950_vsrc>`, :ref:`attr<amdgpu_synid_gfx950_attr>`
+
+VOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`src0<amdgpu_synid_gfx950_src0_1027ca>`
+ v_accvgpr_writelane_regwr_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_clrexcp
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_cvt_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_pk_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_pk_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_exp_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_log_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_mov_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_mov_fed_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_mov_prsv_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_permlane16_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
+ v_permlane32_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
+ v_prng_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_readfirstlane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_59204c>`, :ref:`src0<amdgpu_synid_gfx950_src0_516946>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_screen_partition_4se_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_6802ce>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`
+ v_writelane_regwr_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`
+
+VOP2
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_add_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_addc_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`,:ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_dot2c_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`literal<amdgpu_synid_gfx950_literal_81e671>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_fmac_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`literal<amdgpu_synid_gfx950_literal_81e671>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_madak_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`literal<amdgpu_synid_gfx950_literal_39b593>`
+ v_madmk_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`literal<amdgpu_synid_gfx950_literal_39b593>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_sub_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subb_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`,:ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_subbrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`,:ref:`vcc<amdgpu_synid_gfx950_vcc>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_subrev_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_0f0007>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+
+VOP3
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_add_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_add_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_add_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_ashr_pk_i8_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_ashr_pk_u8_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_bitop3_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_bitop3_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_pk_bf16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pk_bf8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pk_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pk_fp8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_pkaccum_u8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_2xpk16_bf6_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_d52854>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_2xpk16_fp6_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_d52854>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_f16_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_f16_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_bf16_bf6 :ref:`vdst<amdgpu_synid_gfx950_vdst_5f7812>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_bf16_fp6 :ref:`vdst<amdgpu_synid_gfx950_vdst_5f7812>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_bf6_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_bf6_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_f16_bf6 :ref:`vdst<amdgpu_synid_gfx950_vdst_5f7812>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_f16_fp6 :ref:`vdst<amdgpu_synid_gfx950_vdst_5f7812>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_f32_bf6 :ref:`vdst<amdgpu_synid_gfx950_vdst_2eda77>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_f32_fp6 :ref:`vdst<amdgpu_synid_gfx950_vdst_2eda77>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_fp6_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk32_fp6_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_bf16_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_bf16_fp4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_bf16_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_bf8_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_bf8_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_bf8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_pk_f16_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_f16_fp4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_f16_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_f32_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_f32_fp4 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_f32_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_fp4_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_fp4_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_fp4_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_pk_fp8_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_fp8_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_scalef32_pk_fp8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_bf8_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_bf8_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_bf8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_fp8_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_fp8_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_fp8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk32_bf6_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk32_bf6_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk32_bf6_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk32_fp6_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk32_fp6_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk32_fp6_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_363335>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk_fp4_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk_fp4_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_scalef32_sr_pk_fp4_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_cvt_sr_bf16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_sr_bf8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_sr_f16_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_cvt_sr_fp8_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_div_fixup_legacy_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_1db612>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_1db612>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_fma_legacy_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src1<amdgpu_synid_gfx950_src1_6802ce>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`
+ v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src1<amdgpu_synid_gfx950_src1_6802ce>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_interp_p2_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src1<amdgpu_synid_gfx950_src1_6802ce>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_interp_p2_legacy_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src1<amdgpu_synid_gfx950_src1_6802ce>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_lshl_add_u64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_mad_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_mad_legacy_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_legacy_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_legacy_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx950_sdst_3bec61>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_max_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_maximum3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_min_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_minimum3_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_69a144>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e016a1>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_readlane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_59204c>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_43aa79>`
+ v_readlane_regrd_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_59204c>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_43aa79>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_sub_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_sub_i32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_43aa79>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1d4114>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+
+VOP3P
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_accvgpr_read :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_1027ca>`
+ v_accvgpr_wrfed :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`
+ v_accvgpr_write :ref:`vdst<amdgpu_synid_gfx950_vdst_78dd0a>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`
+ v_dot2_f32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_mix_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mad_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_mfma_f32_16x16x128_f8f6f4 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_ca334d>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x16_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x1_4b_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_16x16x32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x32_bf8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x32_bf8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x32_fp8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x32_fp8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x4_4b_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_16x16x4_4b_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_16x16x4_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_16x16x8_xf32 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_32x32x16_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x16_bf8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x16_bf8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x16_fp8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x16_fp8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x1_2b_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_8c77d4>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_a90bd6>`
+ v_mfma_f32_32x32x2_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x4_2b_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_8c77d4>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_a90bd6>`
+ v_mfma_f32_32x32x4_2b_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_8c77d4>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_a90bd6>`
+ v_mfma_f32_32x32x4_xf32 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x64_f8f6f4 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_ca334d>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x8_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_32x32x8_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_f32_4x4x1_16b_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_4x4x4_16b_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f32_4x4x4_16b_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_f64_16x16x4_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_c8d317>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_f36021>`
+ v_mfma_f64_4x4x4_4b_f64 :ref:`vdst<amdgpu_synid_gfx950_vdst_0f48d1>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_1ff383>`
+ v_mfma_i32_16x16x32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_i32_16x16x4_4b_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_i32_16x16x64_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_i32_32x32x16_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_9ad749>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_i32_32x32x32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`
+ v_mfma_i32_32x32x4_2b_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_8c77d4>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_a90bd6>`
+ v_mfma_i32_4x4x4_16b_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`
+ v_mfma_ld_scale_b32 :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_add_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_e30a18>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_14b47a>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_pk_fma_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_e30a18>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`, :ref:`src2<amdgpu_synid_gfx950_src2_e30a18>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_14b47a>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_14b47a>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_maximum3_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_minimum3_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`, :ref:`src2<amdgpu_synid_gfx950_src2_14b47a>`
+ v_pk_mov_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_e30a18>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_mul_f32 :ref:`vdst<amdgpu_synid_gfx950_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx950_src0_e30a18>`, :ref:`src1<amdgpu_synid_gfx950_src1_e30a18>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx950_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx950_src0_168f33>`, :ref:`src1<amdgpu_synid_gfx950_src1_14b47a>`
+ v_smfmac_f32_16x16x128_bf8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x128_bf8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x128_fp8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x128_fp8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x64_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x64_bf8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x64_bf8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x64_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x64_fp8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_16x16x64_fp8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x16_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x16_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x32_bf16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x32_bf8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x32_bf8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x32_f16 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x32_fp8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x32_fp8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x64_bf8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x64_bf8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x64_fp8_bf8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_f32_32x32x64_fp8_fp8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_i32_16x16x128_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_i32_16x16x64_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_i32_32x32x32_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_9ad749>`, :ref:`src1<amdgpu_synid_gfx950_src1_848ff7>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+ v_smfmac_i32_32x32x64_i8 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_848ff7>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_6802ce>`
+
+VOP3PX2
+-------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **SRC4**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_mfma_ld_scale_paired_b32 :ref:`vdst<amdgpu_synid_gfx950_vdst_fa7dbd>`, :ref:`src0<amdgpu_synid_gfx950_src0_be4895>`, :ref:`src1<amdgpu_synid_gfx950_src1_be4895>`, :ref:`src2<amdgpu_synid_gfx950_src2_581e7b>`, :ref:`scale_src0<amdgpu_synid_gfx950_scale_src0>`, :ref:`scale_src1<amdgpu_synid_gfx950_scale_src1>`
+ v_mfma_scale_f32_16x16x128_f8f6f4 :ref:`vdst<amdgpu_synid_gfx950_vdst_180bef>`, :ref:`src0<amdgpu_synid_gfx950_src0_ca334d>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_ca14ce>`, :ref:`scale_src0<amdgpu_synid_gfx950_scale_src0>`, :ref:`scale_src1<amdgpu_synid_gfx950_scale_src1>`
+ v_mfma_scale_f32_32x32x64_f8f6f4 :ref:`vdst<amdgpu_synid_gfx950_vdst_d6f4bd>`, :ref:`src0<amdgpu_synid_gfx950_src0_ca334d>`, :ref:`src1<amdgpu_synid_gfx950_src1_ca334d>`, :ref:`src2<amdgpu_synid_gfx950_src2_14f1c8>`, :ref:`scale_src0<amdgpu_synid_gfx950_scale_src0>`, :ref:`scale_src1<amdgpu_synid_gfx950_scale_src1>`
+
+VOPC
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_f_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_f_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_t_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_t_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_class_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_class_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_class_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_eq_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_eq_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_eq_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_f_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_f_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_f_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_f_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_f_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_f_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_f_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_f_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_f_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_ge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_ge_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ge_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ge_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_ge_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ge_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ge_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_gt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_gt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_gt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_gt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_gt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_gt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_gt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_gt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_gt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_le_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_le_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_le_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_le_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_le_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_le_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_le_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_le_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_le_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_lg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_lt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_lt_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lt_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lt_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_lt_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lt_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_lt_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_ne_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ne_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ne_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_ne_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ne_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ne_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_neq_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_neq_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_neq_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_nge_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nge_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nge_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_ngt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ngt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_ngt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_nle_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nle_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nle_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_nlg_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nlg_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nlg_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_nlt_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nlt_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_nlt_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_o_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_o_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_o_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_t_i16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_t_i32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_t_i64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_t_u16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_t_u32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_t_u64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_tru_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_tru_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_tru_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+ v_cmpx_u_f16 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_u_f32 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_06ee74>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_6802ce>`
+ v_cmpx_u_f64 :ref:`vcc<amdgpu_synid_gfx950_vcc>`, :ref:`src0<amdgpu_synid_gfx950_src0_62f8c2>`, :ref:`vsrc1<amdgpu_synid_gfx950_vsrc1_fd235e>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+.. toctree::
+ :hidden:
+
+ gfx950_addr_c8b8d4
+ gfx950_addr_f2b449
+ gfx950_attr
+ gfx950_data0_848ff7
+ gfx950_data0_9ad749
+ gfx950_data0_be4895
+ gfx950_data0_cfb402
+ gfx950_data1_9ad749
+ gfx950_data1_be4895
+ gfx950_data_848ff7
+ gfx950_data_9ad749
+ gfx950_data_be4895
+ gfx950_data_cfb402
+ gfx950_literal_39b593
+ gfx950_literal_81e671
+ gfx950_saddr_13d69a
+ gfx950_saddr_ce8216
+ gfx950_sbase_010ce0
+ gfx950_sbase_044055
+ gfx950_sbase_0cd545
+ gfx950_scale_src0
+ gfx950_scale_src1
+ gfx950_sdata_0804b1
+ gfx950_sdata_362c37
+ gfx950_sdata_3bc700
+ gfx950_sdata_718cc4
+ gfx950_sdata_94342d
+ gfx950_sdata_aefe00
+ gfx950_sdata_c6aec1
+ gfx950_sdata_d725ab
+ gfx950_sdata_eb6f2a
+ gfx950_sdst_02b357
+ gfx950_sdst_06b266
+ gfx950_sdst_1db612
+ gfx950_sdst_3bec61
+ gfx950_sdst_718cc4
+ gfx950_sdst_94342d
+ gfx950_sdst_a319e6
+ gfx950_simm16_218bea
+ gfx950_simm16_39b593
+ gfx950_simm16_3d2a4f
+ gfx950_simm16_7ed651
+ gfx950_simm16_cc1716
+ gfx950_simm16_ee8b30
+ gfx950_soffset_1189ef
+ gfx950_soffset_8aa27a
+ gfx950_soffset_d856a0
+ gfx950_src0_06ee74
+ gfx950_src0_0f0007
+ gfx950_src0_1027ca
+ gfx950_src0_14b47a
+ gfx950_src0_168f33
+ gfx950_src0_1d4114
+ gfx950_src0_516946
+ gfx950_src0_62f8c2
+ gfx950_src0_6802ce
+ gfx950_src0_848ff7
+ gfx950_src0_9ad749
+ gfx950_src0_be4895
+ gfx950_src0_ca334d
+ gfx950_src0_e30a18
+ gfx950_src1_14b47a
+ gfx950_src1_43aa79
+ gfx950_src1_6802ce
+ gfx950_src1_848ff7
+ gfx950_src1_9ad749
+ gfx950_src1_be4895
+ gfx950_src1_ca334d
+ gfx950_src1_d52854
+ gfx950_src1_e30a18
+ gfx950_src2_14b47a
+ gfx950_src2_14f1c8
+ gfx950_src2_1ff383
+ gfx950_src2_581e7b
+ gfx950_src2_6802ce
+ gfx950_src2_a90bd6
+ gfx950_src2_ca14ce
+ gfx950_src2_e016a1
+ gfx950_src2_e30a18
+ gfx950_src2_f36021
+ gfx950_srsrc_79ffcd
+ gfx950_srsrc_e73d16
+ gfx950_ssamp
+ gfx950_ssrc0_1ce478
+ gfx950_ssrc0_595c25
+ gfx950_ssrc0_83ef5a
+ gfx950_ssrc0_e9f591
+ gfx950_ssrc0_eecc17
+ gfx950_ssrc1_1ce478
+ gfx950_ssrc1_5c7b50
+ gfx950_ssrc1_83ef5a
+ gfx950_ssrc1_eecc17
+ gfx950_tgt
+ gfx950_vaddr_5d0b42
+ gfx950_vaddr_7a736f
+ gfx950_vcc
+ gfx950_vdata_0f48d1
+ gfx950_vdata_180bef
+ gfx950_vdata_260aca
+ gfx950_vdata_2a143d
+ gfx950_vdata_2a60db
+ gfx950_vdata_2d0375
+ gfx950_vdata_576598
+ gfx950_vdata_8e9b87
+ gfx950_vdata_a507a0
+ gfx950_vdata_a5f23e
+ gfx950_vdata_fa7dbd
+ gfx950_vdst_0f48d1
+ gfx950_vdst_180bef
+ gfx950_vdst_260aca
+ gfx950_vdst_2eda77
+ gfx950_vdst_363335
+ gfx950_vdst_59204c
+ gfx950_vdst_5f7812
+ gfx950_vdst_69a144
+ gfx950_vdst_78dd0a
+ gfx950_vdst_89680f
+ gfx950_vdst_8c77d4
+ gfx950_vdst_bdb32f
+ gfx950_vdst_c8d317
+ gfx950_vdst_c8ee02
+ gfx950_vdst_d6f4bd
+ gfx950_vdst_ef6c94
+ gfx950_vdst_fa7dbd
+ gfx950_vsrc
+ gfx950_vsrc0
+ gfx950_vsrc1_6802ce
+ gfx950_vsrc1_fd235e
+ gfx950_vsrc2
+ gfx950_vsrc3
diff --git a/llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst b/llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst
new file mode 100644
index 0000000000000..dd1f1a36f1ee8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_addr_c8b8d4:
+
+addr
+====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_addr_f2b449.rst b/llvm/docs/AMDGPU/gfx950_addr_f2b449.rst
new file mode 100644
index 0000000000000..9ff91c269020f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_addr_f2b449.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_addr_f2b449:
+
+addr
+====
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_attr.rst b/llvm/docs/AMDGPU/gfx950_attr.rst
new file mode 100644
index 0000000000000..a881e17893197
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_attr.rst
@@ -0,0 +1,29 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_attr:
+
+attr
+====
+
+Interpolation attribute and channel:
+
+ ============== ===================================
+ Syntax Description
+ ============== ===================================
+ attr{0..32}.x Attribute 0..32 with *x* channel.
+ attr{0..32}.y Attribute 0..32 with *y* channel.
+ attr{0..32}.z Attribute 0..32 with *z* channel.
+ attr{0..32}.w Attribute 0..32 with *w* channel.
+ ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+ v_interp_p1_f32 v1, v0, attr0.x
+ v_interp_p1_f32 v1, v0, attr32.w
diff --git a/llvm/docs/AMDGPU/gfx950_data0_848ff7.rst b/llvm/docs/AMDGPU/gfx950_data0_848ff7.rst
new file mode 100644
index 0000000000000..3152ac30d901a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data0_848ff7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data0_848ff7:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data0_9ad749.rst b/llvm/docs/AMDGPU/gfx950_data0_9ad749.rst
new file mode 100644
index 0000000000000..36dce93907827
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data0_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data0_9ad749:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data0_be4895.rst b/llvm/docs/AMDGPU/gfx950_data0_be4895.rst
new file mode 100644
index 0000000000000..de58c9a7c1243
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data0_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data0_be4895:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data0_cfb402.rst b/llvm/docs/AMDGPU/gfx950_data0_cfb402.rst
new file mode 100644
index 0000000000000..e7196e6149196
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data0_cfb402.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data0_cfb402:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data1_9ad749.rst b/llvm/docs/AMDGPU/gfx950_data1_9ad749.rst
new file mode 100644
index 0000000000000..279fcd137c40b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data1_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data1_9ad749:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data1_be4895.rst b/llvm/docs/AMDGPU/gfx950_data1_be4895.rst
new file mode 100644
index 0000000000000..5935d74445259
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data1_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data1_be4895:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_848ff7.rst b/llvm/docs/AMDGPU/gfx950_data_848ff7.rst
new file mode 100644
index 0000000000000..8a27f77135047
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data_848ff7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data_848ff7:
+
+data
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_9ad749.rst b/llvm/docs/AMDGPU/gfx950_data_9ad749.rst
new file mode 100644
index 0000000000000..b2af6a362390c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data_9ad749:
+
+data
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_be4895.rst b/llvm/docs/AMDGPU/gfx950_data_be4895.rst
new file mode 100644
index 0000000000000..4b37c73a56a5e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data_be4895:
+
+data
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_cfb402.rst b/llvm/docs/AMDGPU/gfx950_data_cfb402.rst
new file mode 100644
index 0000000000000..5c2946b8ba747
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_data_cfb402.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_data_cfb402:
+
+data
+====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_literal_39b593.rst b/llvm/docs/AMDGPU/gfx950_literal_39b593.rst
new file mode 100644
index 0000000000000..afd32e40d43c8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_literal_39b593.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_literal_39b593:
+
+literal
+=======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
diff --git a/llvm/docs/AMDGPU/gfx950_literal_81e671.rst b/llvm/docs/AMDGPU/gfx950_literal_81e671.rst
new file mode 100644
index 0000000000000..cb656f1aef901
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_literal_81e671.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_literal_81e671:
+
+literal
+=======
+
+*Size:* 1 dword.
+
+*Operands:*
diff --git a/llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst b/llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst
new file mode 100644
index 0000000000000..4939c7df5a33f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_saddr_13d69a:
+
+saddr
+=====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst b/llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst
new file mode 100644
index 0000000000000..2ed2a9d4ddb60
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_saddr_ce8216:
+
+saddr
+=====
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst
new file mode 100644
index 0000000000000..64d4bc7ee2b97
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sbase_010ce0:
+
+sbase
+=====
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sbase_044055.rst b/llvm/docs/AMDGPU/gfx950_sbase_044055.rst
new file mode 100644
index 0000000000000..abf9caf6e3afb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sbase_044055.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sbase_044055:
+
+sbase
+=====
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst b/llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst
new file mode 100644
index 0000000000000..b5498c40f7a78
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sbase_0cd545:
+
+sbase
+=====
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_scale_src0.rst b/llvm/docs/AMDGPU/gfx950_scale_src0.rst
new file mode 100644
index 0000000000000..e721afa8cf462
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_scale_src0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_scale_src0:
+
+scale_src0
+==========
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_scale_src1.rst b/llvm/docs/AMDGPU/gfx950_scale_src1.rst
new file mode 100644
index 0000000000000..137b466b64664
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_scale_src1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_scale_src1:
+
+scale_src1
+==========
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst b/llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst
new file mode 100644
index 0000000000000..72d3181d22ed7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_0804b1:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_362c37.rst b/llvm/docs/AMDGPU/gfx950_sdata_362c37.rst
new file mode 100644
index 0000000000000..4f177a5c70568
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_362c37.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_362c37:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst b/llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst
new file mode 100644
index 0000000000000..7e96e63eb4a4e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_3bc700:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst b/llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst
new file mode 100644
index 0000000000000..93ba7f34452f4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_718cc4:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_94342d.rst b/llvm/docs/AMDGPU/gfx950_sdata_94342d.rst
new file mode 100644
index 0000000000000..2f1a3b5ac0c2d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_94342d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_94342d:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst b/llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst
new file mode 100644
index 0000000000000..941340c436506
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_aefe00:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst b/llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst
new file mode 100644
index 0000000000000..fe6e5d9f31a04
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_c6aec1:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst b/llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst
new file mode 100644
index 0000000000000..d4593ebbd2b7f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_d725ab:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`simm8<amdgpu_synid_simm8>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst b/llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst
new file mode 100644
index 0000000000000..1f81aefaf5dad
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdata_eb6f2a:
+
+sdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_02b357.rst b/llvm/docs/AMDGPU/gfx950_sdst_02b357.rst
new file mode 100644
index 0000000000000..0c1188598ee26
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_02b357.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_02b357:
+
+sdst
+====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_06b266.rst b/llvm/docs/AMDGPU/gfx950_sdst_06b266.rst
new file mode 100644
index 0000000000000..9e2ab5dc9dc71
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_06b266.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_06b266:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_1db612.rst b/llvm/docs/AMDGPU/gfx950_sdst_1db612.rst
new file mode 100644
index 0000000000000..bc9386987670f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_1db612.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_1db612:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst b/llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst
new file mode 100644
index 0000000000000..ec3c04b317d8b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_3bec61:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst b/llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst
new file mode 100644
index 0000000000000..a958a08f65fc3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_718cc4:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_94342d.rst b/llvm/docs/AMDGPU/gfx950_sdst_94342d.rst
new file mode 100644
index 0000000000000..8aa656e00e786
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_94342d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_94342d:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst b/llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst
new file mode 100644
index 0000000000000..4634d757de9a4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_sdst_a319e6:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_218bea.rst b/llvm/docs/AMDGPU/gfx950_simm16_218bea.rst
new file mode 100644
index 0000000000000..f388c0c501d20
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_simm16_218bea.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_simm16_218bea:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`waitcnt<amdgpu_synid_waitcnt>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_39b593.rst b/llvm/docs/AMDGPU/gfx950_simm16_39b593.rst
new file mode 100644
index 0000000000000..3a1db06e3359e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_simm16_39b593.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_simm16_39b593:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst b/llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst
new file mode 100644
index 0000000000000..93e9eb44f25c6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_simm16_3d2a4f:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`label<amdgpu_synid_label>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst b/llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst
new file mode 100644
index 0000000000000..2d44262fa44e9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_simm16_7ed651:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst b/llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst
new file mode 100644
index 0000000000000..4b4462f29f45f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_simm16_cc1716:
+
+simm16
+======
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst b/llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst
new file mode 100644
index 0000000000000..f732b9c43a785
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst
@@ -0,0 +1,15 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_simm16_ee8b30:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`sendmsg<amdgpu_synid_sendmsg>`
diff --git a/llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst b/llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst
new file mode 100644
index 0000000000000..a17343267f53d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_soffset_1189ef:
+
+soffset
+=======
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst b/llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst
new file mode 100644
index 0000000000000..384970d66f960
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_soffset_8aa27a:
+
+soffset
+=======
+
+An unsigned 20-bit offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst b/llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst
new file mode 100644
index 0000000000000..270b6b1b79d7a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_soffset_d856a0:
+
+soffset
+=======
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_06ee74.rst b/llvm/docs/AMDGPU/gfx950_src0_06ee74.rst
new file mode 100644
index 0000000000000..252b827c20a6a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_06ee74.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_06ee74:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_0f0007.rst b/llvm/docs/AMDGPU/gfx950_src0_0f0007.rst
new file mode 100644
index 0000000000000..7db4826a42d56
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_0f0007.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_0f0007:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_1027ca.rst b/llvm/docs/AMDGPU/gfx950_src0_1027ca.rst
new file mode 100644
index 0000000000000..fb6003a13dea1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_1027ca.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_1027ca:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_14b47a.rst b/llvm/docs/AMDGPU/gfx950_src0_14b47a.rst
new file mode 100644
index 0000000000000..868203a9e4402
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_14b47a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_14b47a:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_168f33.rst b/llvm/docs/AMDGPU/gfx950_src0_168f33.rst
new file mode 100644
index 0000000000000..05fb0663f820f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_168f33.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_168f33:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_1d4114.rst b/llvm/docs/AMDGPU/gfx950_src0_1d4114.rst
new file mode 100644
index 0000000000000..23bc6972e9303
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_1d4114.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_1d4114:
+
+src0
+====
+
+attr0.x through attr63.w, parameter attribute and channel to be interpolated
diff --git a/llvm/docs/AMDGPU/gfx950_src0_516946.rst b/llvm/docs/AMDGPU/gfx950_src0_516946.rst
new file mode 100644
index 0000000000000..1a225df1d2047
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_516946.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_516946:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst b/llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst
new file mode 100644
index 0000000000000..19df446fdadc1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_62f8c2:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_6802ce.rst b/llvm/docs/AMDGPU/gfx950_src0_6802ce.rst
new file mode 100644
index 0000000000000..9b9fbc0d9003b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_6802ce:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_848ff7.rst b/llvm/docs/AMDGPU/gfx950_src0_848ff7.rst
new file mode 100644
index 0000000000000..6e8c4246319c1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_848ff7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_848ff7:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_9ad749.rst b/llvm/docs/AMDGPU/gfx950_src0_9ad749.rst
new file mode 100644
index 0000000000000..c63ebcbc235c6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_9ad749:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_be4895.rst b/llvm/docs/AMDGPU/gfx950_src0_be4895.rst
new file mode 100644
index 0000000000000..59332ef491e96
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_be4895:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_ca334d.rst b/llvm/docs/AMDGPU/gfx950_src0_ca334d.rst
new file mode 100644
index 0000000000000..255e9bbbd7121
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_ca334d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_ca334d:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_e30a18.rst b/llvm/docs/AMDGPU/gfx950_src0_e30a18.rst
new file mode 100644
index 0000000000000..c8246863503eb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src0_e30a18.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src0_e30a18:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_14b47a.rst b/llvm/docs/AMDGPU/gfx950_src1_14b47a.rst
new file mode 100644
index 0000000000000..ee25464c48219
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_14b47a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_14b47a:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_43aa79.rst b/llvm/docs/AMDGPU/gfx950_src1_43aa79.rst
new file mode 100644
index 0000000000000..6d6fbf33ee7da
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_43aa79.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_43aa79:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_6802ce.rst b/llvm/docs/AMDGPU/gfx950_src1_6802ce.rst
new file mode 100644
index 0000000000000..08fb2451ecc39
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_6802ce:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_848ff7.rst b/llvm/docs/AMDGPU/gfx950_src1_848ff7.rst
new file mode 100644
index 0000000000000..8f294f2113206
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_848ff7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_848ff7:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_9ad749.rst b/llvm/docs/AMDGPU/gfx950_src1_9ad749.rst
new file mode 100644
index 0000000000000..c1b018263b726
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_9ad749.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_9ad749:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_be4895.rst b/llvm/docs/AMDGPU/gfx950_src1_be4895.rst
new file mode 100644
index 0000000000000..8cfc8ce287e74
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_be4895.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_be4895:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_ca334d.rst b/llvm/docs/AMDGPU/gfx950_src1_ca334d.rst
new file mode 100644
index 0000000000000..a187aa22cd9bb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_ca334d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_ca334d:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_d52854.rst b/llvm/docs/AMDGPU/gfx950_src1_d52854.rst
new file mode 100644
index 0000000000000..6b2c938cfd282
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_d52854.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_d52854:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_e30a18.rst b/llvm/docs/AMDGPU/gfx950_src1_e30a18.rst
new file mode 100644
index 0000000000000..81e35412bdeca
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src1_e30a18.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src1_e30a18:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_14b47a.rst b/llvm/docs/AMDGPU/gfx950_src2_14b47a.rst
new file mode 100644
index 0000000000000..2f0037c709189
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_14b47a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_14b47a:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst b/llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst
new file mode 100644
index 0000000000000..17eb4a2777b60
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_14f1c8:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_1ff383.rst b/llvm/docs/AMDGPU/gfx950_src2_1ff383.rst
new file mode 100644
index 0000000000000..93fabe2aadefc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_1ff383.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_1ff383:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_581e7b.rst b/llvm/docs/AMDGPU/gfx950_src2_581e7b.rst
new file mode 100644
index 0000000000000..5d0deda5f66e1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_581e7b.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_581e7b:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_6802ce.rst b/llvm/docs/AMDGPU/gfx950_src2_6802ce.rst
new file mode 100644
index 0000000000000..01d25c540faec
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_6802ce:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst b/llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst
new file mode 100644
index 0000000000000..90eed3143d3fe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_a90bd6:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst b/llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst
new file mode 100644
index 0000000000000..ba523c038c93c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_ca14ce:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_e016a1.rst b/llvm/docs/AMDGPU/gfx950_src2_e016a1.rst
new file mode 100644
index 0000000000000..4e663e36f215c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_e016a1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_e016a1:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_e30a18.rst b/llvm/docs/AMDGPU/gfx950_src2_e30a18.rst
new file mode 100644
index 0000000000000..7230d26d2a7d1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_e30a18.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_e30a18:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_f36021.rst b/llvm/docs/AMDGPU/gfx950_src2_f36021.rst
new file mode 100644
index 0000000000000..8b7df00e7a693
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_src2_f36021.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_src2_f36021:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst b/llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst
new file mode 100644
index 0000000000000..b91d23ee9462f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_srsrc_79ffcd:
+
+srsrc
+=====
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst b/llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst
new file mode 100644
index 0000000000000..753e7fa7b051c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_srsrc_e73d16:
+
+srsrc
+=====
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssamp.rst b/llvm/docs/AMDGPU/gfx950_ssamp.rst
new file mode 100644
index 0000000000000..c4a8be40baf37
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssamp.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssamp:
+
+ssamp
+=====
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst
new file mode 100644
index 0000000000000..c45b7d115ea50
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc0_1ce478:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst
new file mode 100644
index 0000000000000..682411f7c97fd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc0_595c25:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst
new file mode 100644
index 0000000000000..612f0b9d14448
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc0_83ef5a:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst
new file mode 100644
index 0000000000000..924b74d921927
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc0_e9f591:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst
new file mode 100644
index 0000000000000..c46fb2366804f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc0_eecc17:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst
new file mode 100644
index 0000000000000..5183b65c5b8bf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc1_1ce478:
+
+ssrc1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst
new file mode 100644
index 0000000000000..ef38d9aa57879
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc1_5c7b50:
+
+ssrc1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:*
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst
new file mode 100644
index 0000000000000..ad2cba74e43cc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc1_83ef5a:
+
+ssrc1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst
new file mode 100644
index 0000000000000..74e3c7f237a4c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_ssrc1_eecc17:
+
+ssrc1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_tgt.rst b/llvm/docs/AMDGPU/gfx950_tgt.rst
new file mode 100644
index 0000000000000..3b6b57eec5d71
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_tgt.rst
@@ -0,0 +1,23 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_tgt:
+
+tgt
+===
+
+An export target:
+
+ ================== ===================================
+ Syntax Description
+ ================== ===================================
+ pos{0..3} Copy vertex position 0..3.
+ param{0..31} Copy vertex parameter 0..31.
+ mrt{0..7} Copy pixel color to the MRTs 0..7.
+ mrtz Copy pixel depth (Z) data.
+ null Copy nothing.
+ ================== ===================================
diff --git a/llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst b/llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst
new file mode 100644
index 0000000000000..51f763868b4d6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vaddr_5d0b42:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
+
+ Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
+
+ Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst b/llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst
new file mode 100644
index 0000000000000..ee5fd3993be54
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vaddr_7a736f:
+
+vaddr
+=====
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vcc.rst b/llvm/docs/AMDGPU/gfx950_vcc.rst
new file mode 100644
index 0000000000000..2c19a8ab4df8f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vcc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vcc:
+
+vcc
+===
+
+Vector condition code.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst b/llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst
new file mode 100644
index 0000000000000..9dec3361af660
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_0f48d1:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_180bef.rst b/llvm/docs/AMDGPU/gfx950_vdata_180bef.rst
new file mode 100644
index 0000000000000..6afb8b502a601
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_180bef.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_180bef:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_260aca.rst b/llvm/docs/AMDGPU/gfx950_vdata_260aca.rst
new file mode 100644
index 0000000000000..3f65c2f187655
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_260aca.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_260aca:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst b/llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst
new file mode 100644
index 0000000000000..08b024fe5b7ad
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_2a143d:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst b/llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst
new file mode 100644
index 0000000000000..11fdec6bbb3f7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_2a60db:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst b/llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst
new file mode 100644
index 0000000000000..87ba2f90fb2d8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_2d0375:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_576598.rst b/llvm/docs/AMDGPU/gfx950_vdata_576598.rst
new file mode 100644
index 0000000000000..254e02eef6353
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_576598.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_576598:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst b/llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst
new file mode 100644
index 0000000000000..8704c186bb7ce
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_8e9b87:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst b/llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst
new file mode 100644
index 0000000000000..5e0b841af7acb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_a507a0:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst b/llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst
new file mode 100644
index 0000000000000..dc2758a389ba5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_a5f23e:
+
+vdata
+=====
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst b/llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst
new file mode 100644
index 0000000000000..cd8f11f27f295
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdata_fa7dbd:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst b/llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst
new file mode 100644
index 0000000000000..3904967521937
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_0f48d1:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_180bef.rst b/llvm/docs/AMDGPU/gfx950_vdst_180bef.rst
new file mode 100644
index 0000000000000..b14166040e15d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_180bef.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_180bef:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_260aca.rst b/llvm/docs/AMDGPU/gfx950_vdst_260aca.rst
new file mode 100644
index 0000000000000..d7ddebfc67f81
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_260aca.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_260aca:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst b/llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst
new file mode 100644
index 0000000000000..6c5d6cb4335f4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_2eda77:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_363335.rst b/llvm/docs/AMDGPU/gfx950_vdst_363335.rst
new file mode 100644
index 0000000000000..c75ee383a29d9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_363335.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_363335:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 6 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_59204c.rst b/llvm/docs/AMDGPU/gfx950_vdst_59204c.rst
new file mode 100644
index 0000000000000..05ff98adb7263
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_59204c.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_59204c:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst b/llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst
new file mode 100644
index 0000000000000..6511d6f5c1424
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_5f7812:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_69a144.rst b/llvm/docs/AMDGPU/gfx950_vdst_69a144.rst
new file mode 100644
index 0000000000000..efda05c6dd01d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_69a144.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_69a144:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst b/llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst
new file mode 100644
index 0000000000000..6ad20c423ebb6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_78dd0a:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_89680f.rst b/llvm/docs/AMDGPU/gfx950_vdst_89680f.rst
new file mode 100644
index 0000000000000..58667cbfac975
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_89680f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_89680f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst b/llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst
new file mode 100644
index 0000000000000..efe1da57cb023
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_8c77d4:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst b/llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst
new file mode 100644
index 0000000000000..dbf76e676a946
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_bdb32f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst b/llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst
new file mode 100644
index 0000000000000..0117a7933180c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_c8d317:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst b/llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst
new file mode 100644
index 0000000000000..d87e84b3ced76
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_c8ee02:
+
+vdst
+====
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst b/llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst
new file mode 100644
index 0000000000000..7d515738d8b8f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_d6f4bd:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst b/llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst
new file mode 100644
index 0000000000000..3071ab3c55c7f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_ef6c94:
+
+vdst
+====
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst b/llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst
new file mode 100644
index 0000000000000..b7c6c6c114022
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vdst_fa7dbd:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc.rst b/llvm/docs/AMDGPU/gfx950_vsrc.rst
new file mode 100644
index 0000000000000..aac3cdad06897
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vsrc.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vsrc:
+
+vsrc
+====
+
+Interpolation parameter to read:
+
+ ============ ===================================
+ Syntax Description
+ ============ ===================================
+ p0 Parameter *P0*.
+ p10 Parameter *P10*.
+ p20 Parameter *P20*.
+ ============ ===================================
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc0.rst b/llvm/docs/AMDGPU/gfx950_vsrc0.rst
new file mode 100644
index 0000000000000..d17b0615538f7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vsrc0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vsrc0:
+
+vsrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst b/llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst
new file mode 100644
index 0000000000000..a15ad102091ec
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vsrc1_6802ce:
+
+vsrc1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst b/llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst
new file mode 100644
index 0000000000000..3b89c6984f591
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vsrc1_fd235e:
+
+vsrc1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc2.rst b/llvm/docs/AMDGPU/gfx950_vsrc2.rst
new file mode 100644
index 0000000000000..56d4e0dc3ed1d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vsrc2.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vsrc2:
+
+vsrc2
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc3.rst b/llvm/docs/AMDGPU/gfx950_vsrc3.rst
new file mode 100644
index 0000000000000..5c65b97287d6c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_vsrc3.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_vsrc3:
+
+vsrc3
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 70523faccc395..d4c3a06630cbe 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -17,6 +17,7 @@ User Guide for AMDGPU Backend
AMDGPU/AMDGPUAsmGFX908
AMDGPU/AMDGPUAsmGFX90a
AMDGPU/AMDGPUAsmGFX940
+ AMDGPU/AMDGPUAsmGFX950
AMDGPU/AMDGPUAsmGFX10
AMDGPU/AMDGPUAsmGFX1011
AMDGPU/AMDGPUAsmGFX1013
@@ -20905,6 +20906,8 @@ in this description.
CDNA 3 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx942<AMDGPU/AMDGPUAsmGFX940>`
+ CDNA 4 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx950<AMDGPU/AMDGPUAsmGFX950>`
+
RDNA 1 :doc:`GFX10 RDNA1<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1010<AMDGPU/AMDGPUAsmGFX10>`
:doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>`
>From c2523004a20ae647b03b3f015d49a4e75f6baa2b Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Fri, 6 Mar 2026 10:40:21 -0800
Subject: [PATCH 2/3] Generate a single rst file for the operands instead of
100+ files.
---
llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst | 131 +-
llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst | 15 -
llvm/docs/AMDGPU/gfx950_addr_f2b449.rst | 15 -
llvm/docs/AMDGPU/gfx950_attr.rst | 29 -
llvm/docs/AMDGPU/gfx950_data0_848ff7.rst | 17 -
llvm/docs/AMDGPU/gfx950_data0_9ad749.rst | 17 -
llvm/docs/AMDGPU/gfx950_data0_be4895.rst | 17 -
llvm/docs/AMDGPU/gfx950_data0_cfb402.rst | 17 -
llvm/docs/AMDGPU/gfx950_data1_9ad749.rst | 17 -
llvm/docs/AMDGPU/gfx950_data1_be4895.rst | 17 -
llvm/docs/AMDGPU/gfx950_data_848ff7.rst | 17 -
llvm/docs/AMDGPU/gfx950_data_9ad749.rst | 17 -
llvm/docs/AMDGPU/gfx950_data_be4895.rst | 17 -
llvm/docs/AMDGPU/gfx950_data_cfb402.rst | 17 -
llvm/docs/AMDGPU/gfx950_literal_39b593.rst | 15 -
llvm/docs/AMDGPU/gfx950_literal_81e671.rst | 15 -
llvm/docs/AMDGPU/gfx950_operands.rst | 1495 ++++++++++++++++++++
llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst | 15 -
llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst | 15 -
llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst | 17 -
llvm/docs/AMDGPU/gfx950_sbase_044055.rst | 17 -
llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst | 17 -
llvm/docs/AMDGPU/gfx950_scale_src0.rst | 17 -
llvm/docs/AMDGPU/gfx950_scale_src1.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_362c37.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_94342d.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst | 21 -
llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst | 21 -
llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst | 21 -
llvm/docs/AMDGPU/gfx950_sdst_02b357.rst | 15 -
llvm/docs/AMDGPU/gfx950_sdst_06b266.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdst_1db612.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdst_94342d.rst | 17 -
llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst | 17 -
llvm/docs/AMDGPU/gfx950_simm16_218bea.rst | 15 -
llvm/docs/AMDGPU/gfx950_simm16_39b593.rst | 15 -
llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst | 15 -
llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst | 15 -
llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst | 17 -
llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst | 15 -
llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst | 20 -
llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst | 17 -
llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_06ee74.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_0f0007.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_1027ca.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_14b47a.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_168f33.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_1d4114.rst | 13 -
llvm/docs/AMDGPU/gfx950_src0_516946.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_6802ce.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_848ff7.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_9ad749.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_be4895.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_ca334d.rst | 17 -
llvm/docs/AMDGPU/gfx950_src0_e30a18.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_14b47a.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_43aa79.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_6802ce.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_848ff7.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_9ad749.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_be4895.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_ca334d.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_d52854.rst | 17 -
llvm/docs/AMDGPU/gfx950_src1_e30a18.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_14b47a.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_1ff383.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_581e7b.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_6802ce.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_e016a1.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_e30a18.rst | 17 -
llvm/docs/AMDGPU/gfx950_src2_f36021.rst | 17 -
llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst | 17 -
llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssamp.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst | 17 -
llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst | 17 -
llvm/docs/AMDGPU/gfx950_tgt.rst | 23 -
llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst | 21 -
llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst | 22 -
llvm/docs/AMDGPU/gfx950_vcc.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdata_180bef.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdata_260aca.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst | 26 -
llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst | 21 -
llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst | 21 -
llvm/docs/AMDGPU/gfx950_vdata_576598.rst | 26 -
llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst | 21 -
llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst | 20 -
llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst | 20 -
llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_180bef.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_260aca.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_363335.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_59204c.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_69a144.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_89680f.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst | 19 -
llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst | 17 -
llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst | 19 -
llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst | 17 -
llvm/docs/AMDGPU/gfx950_vsrc.rst | 21 -
llvm/docs/AMDGPU/gfx950_vsrc0.rst | 17 -
llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst | 17 -
llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst | 17 -
llvm/docs/AMDGPU/gfx950_vsrc2.rst | 17 -
llvm/docs/AMDGPU/gfx950_vsrc3.rst | 17 -
132 files changed, 1496 insertions(+), 2398 deletions(-)
delete mode 100644 llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_addr_f2b449.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_attr.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data0_848ff7.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data0_9ad749.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data0_be4895.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data0_cfb402.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data1_9ad749.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data1_be4895.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data_848ff7.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data_9ad749.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data_be4895.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_data_cfb402.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_literal_39b593.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_literal_81e671.rst
create mode 100644 llvm/docs/AMDGPU/gfx950_operands.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sbase_044055.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_scale_src0.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_scale_src1.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_362c37.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_94342d.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_02b357.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_06b266.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_1db612.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_94342d.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_simm16_218bea.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_simm16_39b593.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_06ee74.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_0f0007.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_1027ca.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_14b47a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_168f33.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_1d4114.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_516946.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_6802ce.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_848ff7.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_9ad749.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_be4895.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_ca334d.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src0_e30a18.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_14b47a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_43aa79.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_6802ce.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_848ff7.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_9ad749.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_be4895.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_ca334d.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_d52854.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src1_e30a18.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_14b47a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_1ff383.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_581e7b.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_6802ce.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_e016a1.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_e30a18.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_src2_f36021.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssamp.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_tgt.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vcc.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_180bef.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_260aca.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_576598.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_180bef.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_260aca.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_363335.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_59204c.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_69a144.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_89680f.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vsrc.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vsrc0.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vsrc2.rst
delete mode 100644 llvm/docs/AMDGPU/gfx950_vsrc3.rst
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
index f5f1ece2ffaff..175f82af5596e 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX950.rst
@@ -1617,133 +1617,4 @@ VOPC
.. toctree::
:hidden:
- gfx950_addr_c8b8d4
- gfx950_addr_f2b449
- gfx950_attr
- gfx950_data0_848ff7
- gfx950_data0_9ad749
- gfx950_data0_be4895
- gfx950_data0_cfb402
- gfx950_data1_9ad749
- gfx950_data1_be4895
- gfx950_data_848ff7
- gfx950_data_9ad749
- gfx950_data_be4895
- gfx950_data_cfb402
- gfx950_literal_39b593
- gfx950_literal_81e671
- gfx950_saddr_13d69a
- gfx950_saddr_ce8216
- gfx950_sbase_010ce0
- gfx950_sbase_044055
- gfx950_sbase_0cd545
- gfx950_scale_src0
- gfx950_scale_src1
- gfx950_sdata_0804b1
- gfx950_sdata_362c37
- gfx950_sdata_3bc700
- gfx950_sdata_718cc4
- gfx950_sdata_94342d
- gfx950_sdata_aefe00
- gfx950_sdata_c6aec1
- gfx950_sdata_d725ab
- gfx950_sdata_eb6f2a
- gfx950_sdst_02b357
- gfx950_sdst_06b266
- gfx950_sdst_1db612
- gfx950_sdst_3bec61
- gfx950_sdst_718cc4
- gfx950_sdst_94342d
- gfx950_sdst_a319e6
- gfx950_simm16_218bea
- gfx950_simm16_39b593
- gfx950_simm16_3d2a4f
- gfx950_simm16_7ed651
- gfx950_simm16_cc1716
- gfx950_simm16_ee8b30
- gfx950_soffset_1189ef
- gfx950_soffset_8aa27a
- gfx950_soffset_d856a0
- gfx950_src0_06ee74
- gfx950_src0_0f0007
- gfx950_src0_1027ca
- gfx950_src0_14b47a
- gfx950_src0_168f33
- gfx950_src0_1d4114
- gfx950_src0_516946
- gfx950_src0_62f8c2
- gfx950_src0_6802ce
- gfx950_src0_848ff7
- gfx950_src0_9ad749
- gfx950_src0_be4895
- gfx950_src0_ca334d
- gfx950_src0_e30a18
- gfx950_src1_14b47a
- gfx950_src1_43aa79
- gfx950_src1_6802ce
- gfx950_src1_848ff7
- gfx950_src1_9ad749
- gfx950_src1_be4895
- gfx950_src1_ca334d
- gfx950_src1_d52854
- gfx950_src1_e30a18
- gfx950_src2_14b47a
- gfx950_src2_14f1c8
- gfx950_src2_1ff383
- gfx950_src2_581e7b
- gfx950_src2_6802ce
- gfx950_src2_a90bd6
- gfx950_src2_ca14ce
- gfx950_src2_e016a1
- gfx950_src2_e30a18
- gfx950_src2_f36021
- gfx950_srsrc_79ffcd
- gfx950_srsrc_e73d16
- gfx950_ssamp
- gfx950_ssrc0_1ce478
- gfx950_ssrc0_595c25
- gfx950_ssrc0_83ef5a
- gfx950_ssrc0_e9f591
- gfx950_ssrc0_eecc17
- gfx950_ssrc1_1ce478
- gfx950_ssrc1_5c7b50
- gfx950_ssrc1_83ef5a
- gfx950_ssrc1_eecc17
- gfx950_tgt
- gfx950_vaddr_5d0b42
- gfx950_vaddr_7a736f
- gfx950_vcc
- gfx950_vdata_0f48d1
- gfx950_vdata_180bef
- gfx950_vdata_260aca
- gfx950_vdata_2a143d
- gfx950_vdata_2a60db
- gfx950_vdata_2d0375
- gfx950_vdata_576598
- gfx950_vdata_8e9b87
- gfx950_vdata_a507a0
- gfx950_vdata_a5f23e
- gfx950_vdata_fa7dbd
- gfx950_vdst_0f48d1
- gfx950_vdst_180bef
- gfx950_vdst_260aca
- gfx950_vdst_2eda77
- gfx950_vdst_363335
- gfx950_vdst_59204c
- gfx950_vdst_5f7812
- gfx950_vdst_69a144
- gfx950_vdst_78dd0a
- gfx950_vdst_89680f
- gfx950_vdst_8c77d4
- gfx950_vdst_bdb32f
- gfx950_vdst_c8d317
- gfx950_vdst_c8ee02
- gfx950_vdst_d6f4bd
- gfx950_vdst_ef6c94
- gfx950_vdst_fa7dbd
- gfx950_vsrc
- gfx950_vsrc0
- gfx950_vsrc1_6802ce
- gfx950_vsrc1_fd235e
- gfx950_vsrc2
- gfx950_vsrc3
+ gfx950_operands
diff --git a/llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst b/llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst
deleted file mode 100644
index dd1f1a36f1ee8..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_addr_c8b8d4.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_addr_c8b8d4:
-
-addr
-====
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_addr_f2b449.rst b/llvm/docs/AMDGPU/gfx950_addr_f2b449.rst
deleted file mode 100644
index 9ff91c269020f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_addr_f2b449.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_addr_f2b449:
-
-addr
-====
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_attr.rst b/llvm/docs/AMDGPU/gfx950_attr.rst
deleted file mode 100644
index a881e17893197..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_attr.rst
+++ /dev/null
@@ -1,29 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_attr:
-
-attr
-====
-
-Interpolation attribute and channel:
-
- ============== ===================================
- Syntax Description
- ============== ===================================
- attr{0..32}.x Attribute 0..32 with *x* channel.
- attr{0..32}.y Attribute 0..32 with *y* channel.
- attr{0..32}.z Attribute 0..32 with *z* channel.
- attr{0..32}.w Attribute 0..32 with *w* channel.
- ============== ===================================
-
-Examples:
-
-.. parsed-literal::
-
- v_interp_p1_f32 v1, v0, attr0.x
- v_interp_p1_f32 v1, v0, attr32.w
diff --git a/llvm/docs/AMDGPU/gfx950_data0_848ff7.rst b/llvm/docs/AMDGPU/gfx950_data0_848ff7.rst
deleted file mode 100644
index 3152ac30d901a..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data0_848ff7.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data0_848ff7:
-
-data0
-=====
-
-Instruction input.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data0_9ad749.rst b/llvm/docs/AMDGPU/gfx950_data0_9ad749.rst
deleted file mode 100644
index 36dce93907827..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data0_9ad749.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data0_9ad749:
-
-data0
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data0_be4895.rst b/llvm/docs/AMDGPU/gfx950_data0_be4895.rst
deleted file mode 100644
index de58c9a7c1243..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data0_be4895.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data0_be4895:
-
-data0
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data0_cfb402.rst b/llvm/docs/AMDGPU/gfx950_data0_cfb402.rst
deleted file mode 100644
index e7196e6149196..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data0_cfb402.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data0_cfb402:
-
-data0
-=====
-
-Instruction input.
-
-*Size:* 3 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data1_9ad749.rst b/llvm/docs/AMDGPU/gfx950_data1_9ad749.rst
deleted file mode 100644
index 279fcd137c40b..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data1_9ad749.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data1_9ad749:
-
-data1
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data1_be4895.rst b/llvm/docs/AMDGPU/gfx950_data1_be4895.rst
deleted file mode 100644
index 5935d74445259..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data1_be4895.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data1_be4895:
-
-data1
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_848ff7.rst b/llvm/docs/AMDGPU/gfx950_data_848ff7.rst
deleted file mode 100644
index 8a27f77135047..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data_848ff7.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data_848ff7:
-
-data
-====
-
-Instruction input.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_9ad749.rst b/llvm/docs/AMDGPU/gfx950_data_9ad749.rst
deleted file mode 100644
index b2af6a362390c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data_9ad749.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data_9ad749:
-
-data
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_be4895.rst b/llvm/docs/AMDGPU/gfx950_data_be4895.rst
deleted file mode 100644
index 4b37c73a56a5e..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data_be4895.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data_be4895:
-
-data
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_data_cfb402.rst b/llvm/docs/AMDGPU/gfx950_data_cfb402.rst
deleted file mode 100644
index 5c2946b8ba747..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_data_cfb402.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_data_cfb402:
-
-data
-====
-
-Instruction input.
-
-*Size:* 3 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_literal_39b593.rst b/llvm/docs/AMDGPU/gfx950_literal_39b593.rst
deleted file mode 100644
index afd32e40d43c8..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_literal_39b593.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_literal_39b593:
-
-literal
-=======
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
diff --git a/llvm/docs/AMDGPU/gfx950_literal_81e671.rst b/llvm/docs/AMDGPU/gfx950_literal_81e671.rst
deleted file mode 100644
index cb656f1aef901..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_literal_81e671.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_literal_81e671:
-
-literal
-=======
-
-*Size:* 1 dword.
-
-*Operands:*
diff --git a/llvm/docs/AMDGPU/gfx950_operands.rst b/llvm/docs/AMDGPU/gfx950_operands.rst
new file mode 100644
index 0000000000000..2035df9ce5128
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx950_operands.rst
@@ -0,0 +1,1495 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx950_addr_c8b8d4:
+
+addr
+----
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_addr_f2b449:
+
+addr
+----
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_attr:
+
+attr
+----
+
+Interpolation attribute and channel:
+
+ ============== ===================================
+ Syntax Description
+ ============== ===================================
+ attr{0..32}.x Attribute 0..32 with *x* channel.
+ attr{0..32}.y Attribute 0..32 with *y* channel.
+ attr{0..32}.z Attribute 0..32 with *z* channel.
+ attr{0..32}.w Attribute 0..32 with *w* channel.
+ ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+ v_interp_p1_f32 v1, v0, attr0.x
+ v_interp_p1_f32 v1, v0, attr32.w
+
+.. _amdgpu_synid_gfx950_data_be4895:
+
+data
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data_9ad749:
+
+data
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data_cfb402:
+
+data
+----
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data_848ff7:
+
+data
+----
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data0_be4895:
+
+data0
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data0_9ad749:
+
+data0
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data0_cfb402:
+
+data0
+-----
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data0_848ff7:
+
+data0
+-----
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data1_be4895:
+
+data1
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_data1_9ad749:
+
+data1
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_literal_81e671:
+
+literal
+-------
+
+*Size:* 1 dword.
+
+*Operands:*
+
+.. _amdgpu_synid_gfx950_literal_39b593:
+
+literal
+-------
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
+
+.. _amdgpu_synid_gfx950_saddr_13d69a:
+
+saddr
+-----
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_saddr_ce8216:
+
+saddr
+-----
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sbase_010ce0:
+
+sbase
+-----
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sbase_044055:
+
+sbase
+-----
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sbase_0cd545:
+
+sbase
+-----
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_scale_src0:
+
+scale_src0
+----------
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_scale_src1:
+
+scale_src1
+----------
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_sdata_aefe00:
+
+sdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_eb6f2a:
+
+sdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_c6aec1:
+
+sdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_94342d:
+
+sdata
+-----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_d725ab:
+
+sdata
+-----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`simm8<amdgpu_synid_simm8>`
+
+.. _amdgpu_synid_gfx950_sdata_3bc700:
+
+sdata
+-----
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_718cc4:
+
+sdata
+-----
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_0804b1:
+
+sdata
+-----
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdata_362c37:
+
+sdata
+-----
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdst_02b357:
+
+sdst
+----
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+
+.. _amdgpu_synid_gfx950_sdst_3bec61:
+
+sdst
+----
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdst_1db612:
+
+sdst
+----
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
+
+.. _amdgpu_synid_gfx950_sdst_94342d:
+
+sdst
+----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdst_06b266:
+
+sdst
+----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+
+.. _amdgpu_synid_gfx950_sdst_718cc4:
+
+sdst
+----
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_sdst_a319e6:
+
+sdst
+----
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
+
+.. _amdgpu_synid_gfx950_simm16_7ed651:
+
+simm16
+------
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
+
+.. _amdgpu_synid_gfx950_simm16_39b593:
+
+simm16
+------
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
+
+.. _amdgpu_synid_gfx950_simm16_3d2a4f:
+
+simm16
+------
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`label<amdgpu_synid_label>`
+
+.. _amdgpu_synid_gfx950_simm16_ee8b30:
+
+simm16
+------
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`sendmsg<amdgpu_synid_sendmsg>`
+
+.. _amdgpu_synid_gfx950_simm16_218bea:
+
+simm16
+------
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`waitcnt<amdgpu_synid_waitcnt>`
+
+.. _amdgpu_synid_gfx950_simm16_cc1716:
+
+simm16
+------
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
+
+.. _amdgpu_synid_gfx950_soffset_1189ef:
+
+soffset
+-------
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
+
+.. _amdgpu_synid_gfx950_soffset_8aa27a:
+
+soffset
+-------
+
+An unsigned 20-bit offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
+
+.. _amdgpu_synid_gfx950_soffset_d856a0:
+
+soffset
+-------
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src0_1027ca:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src0_6802ce:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_src0_be4895:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src0_516946:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
+
+.. _amdgpu_synid_gfx950_src0_14b47a:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src0_0f0007:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_src0_168f33:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src0_06ee74:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_src0_9ad749:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src0_e30a18:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src0_62f8c2:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_src0_848ff7:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src0_ca334d:
+
+src0
+----
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src0_1d4114:
+
+src0
+----
+
+attr0.x through attr63.w, parameter attribute and channel to be interpolated
+
+.. _amdgpu_synid_gfx950_src1_43aa79:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
+
+.. _amdgpu_synid_gfx950_src1_6802ce:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_src1_be4895:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src1_14b47a:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src1_d52854:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_src1_9ad749:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src1_e30a18:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src1_848ff7:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src1_ca334d:
+
+src1
+----
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_src2_6802ce:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_src2_581e7b:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_14b47a:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_14f1c8:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_1ff383:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_e30a18:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_a90bd6:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_e016a1:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_src2_ca14ce:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_src2_f36021:
+
+src2
+----
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_srsrc_e73d16:
+
+srsrc
+-----
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_srsrc_79ffcd:
+
+srsrc
+-----
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_ssamp:
+
+ssamp
+-----
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_ssrc0_595c25:
+
+ssrc0
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_ssrc0_eecc17:
+
+ssrc0
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_ssrc0_e9f591:
+
+ssrc0
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_ssrc0_1ce478:
+
+ssrc0
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_ssrc0_83ef5a:
+
+ssrc0
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_ssrc1_5c7b50:
+
+ssrc1
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:*
+
+.. _amdgpu_synid_gfx950_ssrc1_eecc17:
+
+ssrc1
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_ssrc1_1ce478:
+
+ssrc1
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
+
+.. _amdgpu_synid_gfx950_ssrc1_83ef5a:
+
+ssrc1
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
+
+.. _amdgpu_synid_gfx950_tgt:
+
+tgt
+---
+
+An export target:
+
+ ================== ===================================
+ Syntax Description
+ ================== ===================================
+ pos{0..3} Copy vertex position 0..3.
+ param{0..31} Copy vertex parameter 0..31.
+ mrt{0..7} Copy pixel color to the MRTs 0..7.
+ mrtz Copy pixel depth (Z) data.
+ null Copy nothing.
+ ================== ===================================
+
+.. _amdgpu_synid_gfx950_vaddr_5d0b42:
+
+vaddr
+-----
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
+
+ Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
+
+ Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vaddr_7a736f:
+
+vaddr
+-----
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vcc:
+
+vcc
+---
+
+Vector condition code.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
+
+.. _amdgpu_synid_gfx950_vdata_a5f23e:
+
+vdata
+-----
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_2a60db:
+
+vdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_2d0375:
+
+vdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_8e9b87:
+
+vdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_2a143d:
+
+vdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_576598:
+
+vdata
+-----
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_fa7dbd:
+
+vdata
+-----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_0f48d1:
+
+vdata
+-----
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_260aca:
+
+vdata
+-----
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_180bef:
+
+vdata
+-----
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdata_a507a0:
+
+vdata
+-----
+
+Instruction output.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_c8ee02:
+
+vdst
+----
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_ef6c94:
+
+vdst
+----
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_78dd0a:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_59204c:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+
+.. _amdgpu_synid_gfx950_vdst_89680f:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vdst_fa7dbd:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_5f7812:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vdst_d6f4bd:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_bdb32f:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vdst_0f48d1:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_260aca:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_2eda77:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vdst_8c77d4:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_69a144:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vdst_180bef:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vdst_363335:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 6 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vdst_c8d317:
+
+vdst
+----
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
+
+.. _amdgpu_synid_gfx950_vsrc:
+
+vsrc
+----
+
+Interpolation parameter to read:
+
+ ============ ===================================
+ Syntax Description
+ ============ ===================================
+ p0 Parameter *P0*.
+ p10 Parameter *P10*.
+ p20 Parameter *P20*.
+ ============ ===================================
+
+.. _amdgpu_synid_gfx950_vsrc0:
+
+vsrc0
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vsrc1_6802ce:
+
+vsrc1
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vsrc1_fd235e:
+
+vsrc1
+-----
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vsrc2:
+
+vsrc2
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
+.. _amdgpu_synid_gfx950_vsrc3:
+
+vsrc3
+-----
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
+
diff --git a/llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst b/llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst
deleted file mode 100644
index 4939c7df5a33f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_saddr_13d69a.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_saddr_13d69a:
-
-saddr
-=====
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst b/llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst
deleted file mode 100644
index 2ed2a9d4ddb60..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_saddr_ce8216.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_saddr_ce8216:
-
-saddr
-=====
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst
deleted file mode 100644
index 64d4bc7ee2b97..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sbase_010ce0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sbase_010ce0:
-
-sbase
-=====
-
-A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sbase_044055.rst b/llvm/docs/AMDGPU/gfx950_sbase_044055.rst
deleted file mode 100644
index abf9caf6e3afb..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sbase_044055.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sbase_044055:
-
-sbase
-=====
-
-A 64-bit base address for scalar memory operations.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst b/llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst
deleted file mode 100644
index b5498c40f7a78..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sbase_0cd545.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sbase_0cd545:
-
-sbase
-=====
-
-This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_scale_src0.rst b/llvm/docs/AMDGPU/gfx950_scale_src0.rst
deleted file mode 100644
index e721afa8cf462..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_scale_src0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_scale_src0:
-
-scale_src0
-==========
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_scale_src1.rst b/llvm/docs/AMDGPU/gfx950_scale_src1.rst
deleted file mode 100644
index 137b466b64664..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_scale_src1.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_scale_src1:
-
-scale_src1
-==========
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst b/llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst
deleted file mode 100644
index 72d3181d22ed7..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_0804b1.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_0804b1:
-
-sdata
-=====
-
-Instruction output.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_362c37.rst b/llvm/docs/AMDGPU/gfx950_sdata_362c37.rst
deleted file mode 100644
index 4f177a5c70568..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_362c37.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_362c37:
-
-sdata
-=====
-
-Instruction output.
-
-*Size:* 8 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst b/llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst
deleted file mode 100644
index 7e96e63eb4a4e..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_3bc700.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_3bc700:
-
-sdata
-=====
-
-Instruction output.
-
-*Size:* 16 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst b/llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst
deleted file mode 100644
index 93ba7f34452f4..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_718cc4.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_718cc4:
-
-sdata
-=====
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_94342d.rst b/llvm/docs/AMDGPU/gfx950_sdata_94342d.rst
deleted file mode 100644
index 2f1a3b5ac0c2d..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_94342d.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_94342d:
-
-sdata
-=====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst b/llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst
deleted file mode 100644
index 941340c436506..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_aefe00.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_aefe00:
-
-sdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst b/llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst
deleted file mode 100644
index fe6e5d9f31a04..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_c6aec1.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_c6aec1:
-
-sdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst b/llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst
deleted file mode 100644
index d4593ebbd2b7f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_d725ab.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_d725ab:
-
-sdata
-=====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`simm8<amdgpu_synid_simm8>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst b/llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst
deleted file mode 100644
index 1f81aefaf5dad..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdata_eb6f2a.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdata_eb6f2a:
-
-sdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_02b357.rst b/llvm/docs/AMDGPU/gfx950_sdst_02b357.rst
deleted file mode 100644
index 0c1188598ee26..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_02b357.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_02b357:
-
-sdst
-====
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_06b266.rst b/llvm/docs/AMDGPU/gfx950_sdst_06b266.rst
deleted file mode 100644
index 9e2ab5dc9dc71..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_06b266.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_06b266:
-
-sdst
-====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_1db612.rst b/llvm/docs/AMDGPU/gfx950_sdst_1db612.rst
deleted file mode 100644
index bc9386987670f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_1db612.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_1db612:
-
-sdst
-====
-
-Instruction output.
-
-*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
-
-*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst b/llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst
deleted file mode 100644
index ec3c04b317d8b..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_3bec61.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_3bec61:
-
-sdst
-====
-
-Instruction output.
-
-*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst b/llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst
deleted file mode 100644
index a958a08f65fc3..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_718cc4.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_718cc4:
-
-sdst
-====
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_94342d.rst b/llvm/docs/AMDGPU/gfx950_sdst_94342d.rst
deleted file mode 100644
index 8aa656e00e786..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_94342d.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_94342d:
-
-sdst
-====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst b/llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst
deleted file mode 100644
index 4634d757de9a4..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_sdst_a319e6.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_sdst_a319e6:
-
-sdst
-====
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_218bea.rst b/llvm/docs/AMDGPU/gfx950_simm16_218bea.rst
deleted file mode 100644
index f388c0c501d20..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_simm16_218bea.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_simm16_218bea:
-
-simm16
-======
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`waitcnt<amdgpu_synid_waitcnt>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_39b593.rst b/llvm/docs/AMDGPU/gfx950_simm16_39b593.rst
deleted file mode 100644
index 3a1db06e3359e..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_simm16_39b593.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_simm16_39b593:
-
-simm16
-======
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst b/llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst
deleted file mode 100644
index 93e9eb44f25c6..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_simm16_3d2a4f.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_simm16_3d2a4f:
-
-simm16
-======
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`label<amdgpu_synid_label>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst b/llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst
deleted file mode 100644
index 2d44262fa44e9..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_simm16_7ed651.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_simm16_7ed651:
-
-simm16
-======
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst b/llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst
deleted file mode 100644
index 4b4462f29f45f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_simm16_cc1716.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_simm16_cc1716:
-
-simm16
-======
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
diff --git a/llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst b/llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst
deleted file mode 100644
index f732b9c43a785..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_simm16_ee8b30.rst
+++ /dev/null
@@ -1,15 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_simm16_ee8b30:
-
-simm16
-======
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`sendmsg<amdgpu_synid_sendmsg>`
diff --git a/llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst b/llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst
deleted file mode 100644
index a17343267f53d..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_soffset_1189ef.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_soffset_1189ef:
-
-soffset
-=======
-
-An offset added to the base address to get memory address.
-
-* If offset is specified as a register, it supplies an unsigned byte offset.
-* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst b/llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst
deleted file mode 100644
index 384970d66f960..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_soffset_8aa27a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_soffset_8aa27a:
-
-soffset
-=======
-
-An unsigned 20-bit offset added to the base address to get memory address.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst b/llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst
deleted file mode 100644
index 270b6b1b79d7a..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_soffset_d856a0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_soffset_d856a0:
-
-soffset
-=======
-
-An unsigned byte offset.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_06ee74.rst b/llvm/docs/AMDGPU/gfx950_src0_06ee74.rst
deleted file mode 100644
index 252b827c20a6a..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_06ee74.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_06ee74:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_0f0007.rst b/llvm/docs/AMDGPU/gfx950_src0_0f0007.rst
deleted file mode 100644
index 7db4826a42d56..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_0f0007.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_0f0007:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_1027ca.rst b/llvm/docs/AMDGPU/gfx950_src0_1027ca.rst
deleted file mode 100644
index fb6003a13dea1..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_1027ca.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_1027ca:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_14b47a.rst b/llvm/docs/AMDGPU/gfx950_src0_14b47a.rst
deleted file mode 100644
index 868203a9e4402..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_14b47a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_14b47a:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_168f33.rst b/llvm/docs/AMDGPU/gfx950_src0_168f33.rst
deleted file mode 100644
index 05fb0663f820f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_168f33.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_168f33:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_1d4114.rst b/llvm/docs/AMDGPU/gfx950_src0_1d4114.rst
deleted file mode 100644
index 23bc6972e9303..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_1d4114.rst
+++ /dev/null
@@ -1,13 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_1d4114:
-
-src0
-====
-
-attr0.x through attr63.w, parameter attribute and channel to be interpolated
diff --git a/llvm/docs/AMDGPU/gfx950_src0_516946.rst b/llvm/docs/AMDGPU/gfx950_src0_516946.rst
deleted file mode 100644
index 1a225df1d2047..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_516946.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_516946:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst b/llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst
deleted file mode 100644
index 19df446fdadc1..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_62f8c2.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_62f8c2:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_6802ce.rst b/llvm/docs/AMDGPU/gfx950_src0_6802ce.rst
deleted file mode 100644
index 9b9fbc0d9003b..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_6802ce.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_6802ce:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_848ff7.rst b/llvm/docs/AMDGPU/gfx950_src0_848ff7.rst
deleted file mode 100644
index 6e8c4246319c1..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_848ff7.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_848ff7:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_9ad749.rst b/llvm/docs/AMDGPU/gfx950_src0_9ad749.rst
deleted file mode 100644
index c63ebcbc235c6..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_9ad749.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_9ad749:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_be4895.rst b/llvm/docs/AMDGPU/gfx950_src0_be4895.rst
deleted file mode 100644
index 59332ef491e96..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_be4895.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_be4895:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_ca334d.rst b/llvm/docs/AMDGPU/gfx950_src0_ca334d.rst
deleted file mode 100644
index 255e9bbbd7121..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_ca334d.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_ca334d:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 8 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src0_e30a18.rst b/llvm/docs/AMDGPU/gfx950_src0_e30a18.rst
deleted file mode 100644
index c8246863503eb..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src0_e30a18.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src0_e30a18:
-
-src0
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_14b47a.rst b/llvm/docs/AMDGPU/gfx950_src1_14b47a.rst
deleted file mode 100644
index ee25464c48219..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_14b47a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_14b47a:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_43aa79.rst b/llvm/docs/AMDGPU/gfx950_src1_43aa79.rst
deleted file mode 100644
index 6d6fbf33ee7da..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_43aa79.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_43aa79:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_6802ce.rst b/llvm/docs/AMDGPU/gfx950_src1_6802ce.rst
deleted file mode 100644
index 08fb2451ecc39..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_6802ce.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_6802ce:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_848ff7.rst b/llvm/docs/AMDGPU/gfx950_src1_848ff7.rst
deleted file mode 100644
index 8f294f2113206..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_848ff7.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_848ff7:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_9ad749.rst b/llvm/docs/AMDGPU/gfx950_src1_9ad749.rst
deleted file mode 100644
index c1b018263b726..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_9ad749.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_9ad749:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_be4895.rst b/llvm/docs/AMDGPU/gfx950_src1_be4895.rst
deleted file mode 100644
index 8cfc8ce287e74..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_be4895.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_be4895:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_ca334d.rst b/llvm/docs/AMDGPU/gfx950_src1_ca334d.rst
deleted file mode 100644
index a187aa22cd9bb..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_ca334d.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_ca334d:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 8 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_d52854.rst b/llvm/docs/AMDGPU/gfx950_src1_d52854.rst
deleted file mode 100644
index 6b2c938cfd282..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_d52854.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_d52854:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 16 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src1_e30a18.rst b/llvm/docs/AMDGPU/gfx950_src1_e30a18.rst
deleted file mode 100644
index 81e35412bdeca..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src1_e30a18.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src1_e30a18:
-
-src1
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_14b47a.rst b/llvm/docs/AMDGPU/gfx950_src2_14b47a.rst
deleted file mode 100644
index 2f0037c709189..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_14b47a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_14b47a:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst b/llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst
deleted file mode 100644
index 17eb4a2777b60..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_14f1c8.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_14f1c8:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 16 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_1ff383.rst b/llvm/docs/AMDGPU/gfx950_src2_1ff383.rst
deleted file mode 100644
index 93fabe2aadefc..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_1ff383.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_1ff383:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_581e7b.rst b/llvm/docs/AMDGPU/gfx950_src2_581e7b.rst
deleted file mode 100644
index 5d0deda5f66e1..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_581e7b.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_581e7b:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_6802ce.rst b/llvm/docs/AMDGPU/gfx950_src2_6802ce.rst
deleted file mode 100644
index 01d25c540faec..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_6802ce.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_6802ce:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst b/llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst
deleted file mode 100644
index 90eed3143d3fe..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_a90bd6.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_a90bd6:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 32 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst b/llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst
deleted file mode 100644
index ba523c038c93c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_ca14ce.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_ca14ce:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_e016a1.rst b/llvm/docs/AMDGPU/gfx950_src2_e016a1.rst
deleted file mode 100644
index 4e663e36f215c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_e016a1.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_e016a1:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_e30a18.rst b/llvm/docs/AMDGPU/gfx950_src2_e30a18.rst
deleted file mode 100644
index 7230d26d2a7d1..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_e30a18.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_e30a18:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_src2_f36021.rst b/llvm/docs/AMDGPU/gfx950_src2_f36021.rst
deleted file mode 100644
index 8b7df00e7a693..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_src2_f36021.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_src2_f36021:
-
-src2
-====
-
-Instruction input.
-
-*Size:* 8 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst b/llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst
deleted file mode 100644
index b91d23ee9462f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_srsrc_79ffcd.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_srsrc_79ffcd:
-
-srsrc
-=====
-
-Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
-
-*Size:* 8 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst b/llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst
deleted file mode 100644
index 753e7fa7b051c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_srsrc_e73d16.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_srsrc_e73d16:
-
-srsrc
-=====
-
-Buffer resource constant which defines the address and characteristics of the buffer in memory.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssamp.rst b/llvm/docs/AMDGPU/gfx950_ssamp.rst
deleted file mode 100644
index c4a8be40baf37..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssamp.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssamp:
-
-ssamp
-=====
-
-Sampler constant used to specify filtering options applied to the image data after it is read.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst
deleted file mode 100644
index c45b7d115ea50..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc0_1ce478.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc0_1ce478:
-
-ssrc0
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst
deleted file mode 100644
index 682411f7c97fd..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc0_595c25.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc0_595c25:
-
-ssrc0
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst
deleted file mode 100644
index 612f0b9d14448..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc0_83ef5a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc0_83ef5a:
-
-ssrc0
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst
deleted file mode 100644
index 924b74d921927..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc0_e9f591.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc0_e9f591:
-
-ssrc0
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst b/llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst
deleted file mode 100644
index c46fb2366804f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc0_eecc17.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc0_eecc17:
-
-ssrc0
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst
deleted file mode 100644
index 5183b65c5b8bf..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc1_1ce478.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc1_1ce478:
-
-ssrc1
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst
deleted file mode 100644
index ef38d9aa57879..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc1_5c7b50.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc1_5c7b50:
-
-ssrc1
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:*
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst
deleted file mode 100644
index ad2cba74e43cc..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc1_83ef5a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc1_83ef5a:
-
-ssrc1
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst b/llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst
deleted file mode 100644
index 74e3c7f237a4c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_ssrc1_eecc17.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_ssrc1_eecc17:
-
-ssrc1
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx950_tgt.rst b/llvm/docs/AMDGPU/gfx950_tgt.rst
deleted file mode 100644
index 3b6b57eec5d71..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_tgt.rst
+++ /dev/null
@@ -1,23 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_tgt:
-
-tgt
-===
-
-An export target:
-
- ================== ===================================
- Syntax Description
- ================== ===================================
- pos{0..3} Copy vertex position 0..3.
- param{0..31} Copy vertex parameter 0..31.
- mrt{0..7} Copy pixel color to the MRTs 0..7.
- mrtz Copy pixel depth (Z) data.
- null Copy nothing.
- ================== ===================================
diff --git a/llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst b/llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst
deleted file mode 100644
index 51f763868b4d6..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vaddr_5d0b42.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vaddr_5d0b42:
-
-vaddr
-=====
-
-Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
-
-*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
-
- Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
-
- Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst b/llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst
deleted file mode 100644
index ee5fd3993be54..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vaddr_7a736f.rst
+++ /dev/null
@@ -1,22 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vaddr_7a736f:
-
-vaddr
-=====
-
-This is an optional operand which may specify offset and/or index.
-
-*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
-
-* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
-* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
-* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
-* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vcc.rst b/llvm/docs/AMDGPU/gfx950_vcc.rst
deleted file mode 100644
index 2c19a8ab4df8f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vcc.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vcc:
-
-vcc
-===
-
-Vector condition code.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst b/llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst
deleted file mode 100644
index 9dec3361af660..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_0f48d1.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_0f48d1:
-
-vdata
-=====
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_180bef.rst b/llvm/docs/AMDGPU/gfx950_vdata_180bef.rst
deleted file mode 100644
index 6afb8b502a601..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_180bef.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_180bef:
-
-vdata
-=====
-
-Instruction output.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_260aca.rst b/llvm/docs/AMDGPU/gfx950_vdata_260aca.rst
deleted file mode 100644
index 3f65c2f187655..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_260aca.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_260aca:
-
-vdata
-=====
-
-Instruction output.
-
-*Size:* 3 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst b/llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst
deleted file mode 100644
index 08b024fe5b7ad..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_2a143d.rst
+++ /dev/null
@@ -1,26 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_2a143d:
-
-vdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
-
-* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
-* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
- Note: the surface data format is indicated in the image resource constant but not in the instruction.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst b/llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst
deleted file mode 100644
index 11fdec6bbb3f7..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_2a60db.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_2a60db:
-
-vdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst b/llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst
deleted file mode 100644
index 87ba2f90fb2d8..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_2d0375.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_2d0375:
-
-vdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_576598.rst b/llvm/docs/AMDGPU/gfx950_vdata_576598.rst
deleted file mode 100644
index 254e02eef6353..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_576598.rst
+++ /dev/null
@@ -1,26 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_576598:
-
-vdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
-
-* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
-* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
-
- Note: the surface data format is indicated in the image resource constant but not in the instruction.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst b/llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst
deleted file mode 100644
index 8704c186bb7ce..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_8e9b87.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_8e9b87:
-
-vdata
-=====
-
-Input data for an atomic instruction.
-
-Optionally may serve as an output data:
-
-* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst b/llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst
deleted file mode 100644
index 5e0b841af7acb..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_a507a0.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_a507a0:
-
-vdata
-=====
-
-Instruction output.
-
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
-
-* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
-* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst b/llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst
deleted file mode 100644
index dc2758a389ba5..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_a5f23e.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_a5f23e:
-
-vdata
-=====
-
-Image data to store by an *image_store* instruction.
-
-*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
-
-* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
-* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst b/llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst
deleted file mode 100644
index cd8f11f27f295..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdata_fa7dbd.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdata_fa7dbd:
-
-vdata
-=====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst b/llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst
deleted file mode 100644
index 3904967521937..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_0f48d1.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_0f48d1:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_180bef.rst b/llvm/docs/AMDGPU/gfx950_vdst_180bef.rst
deleted file mode 100644
index b14166040e15d..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_180bef.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_180bef:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_260aca.rst b/llvm/docs/AMDGPU/gfx950_vdst_260aca.rst
deleted file mode 100644
index d7ddebfc67f81..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_260aca.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_260aca:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 3 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst b/llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst
deleted file mode 100644
index 6c5d6cb4335f4..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_2eda77.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_2eda77:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 32 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_363335.rst b/llvm/docs/AMDGPU/gfx950_vdst_363335.rst
deleted file mode 100644
index c75ee383a29d9..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_363335.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_363335:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 6 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_59204c.rst b/llvm/docs/AMDGPU/gfx950_vdst_59204c.rst
deleted file mode 100644
index 05ff98adb7263..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_59204c.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_59204c:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst b/llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst
deleted file mode 100644
index 6511d6f5c1424..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_5f7812.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_5f7812:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 16 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_69a144.rst b/llvm/docs/AMDGPU/gfx950_vdst_69a144.rst
deleted file mode 100644
index efda05c6dd01d..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_69a144.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_69a144:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 4 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst b/llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst
deleted file mode 100644
index 6ad20c423ebb6..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_78dd0a.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_78dd0a:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_89680f.rst b/llvm/docs/AMDGPU/gfx950_vdst_89680f.rst
deleted file mode 100644
index 58667cbfac975..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_89680f.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_89680f:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst b/llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst
deleted file mode 100644
index efe1da57cb023..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_8c77d4.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_8c77d4:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 32 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst b/llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst
deleted file mode 100644
index dbf76e676a946..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_bdb32f.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_bdb32f:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst b/llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst
deleted file mode 100644
index 0117a7933180c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_c8d317.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_c8d317:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 8 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst b/llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst
deleted file mode 100644
index d87e84b3ced76..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_c8ee02.rst
+++ /dev/null
@@ -1,19 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_c8ee02:
-
-vdst
-====
-
-Data returned by a 32-bit atomic flat instruction.
-
-This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst b/llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst
deleted file mode 100644
index 7d515738d8b8f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_d6f4bd.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_d6f4bd:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 16 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst b/llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst
deleted file mode 100644
index 3071ab3c55c7f..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_ef6c94.rst
+++ /dev/null
@@ -1,19 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_ef6c94:
-
-vdst
-====
-
-Data returned by a 64-bit atomic flat instruction.
-
-This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst b/llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst
deleted file mode 100644
index b7c6c6c114022..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vdst_fa7dbd.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vdst_fa7dbd:
-
-vdst
-====
-
-Instruction output.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc.rst b/llvm/docs/AMDGPU/gfx950_vsrc.rst
deleted file mode 100644
index aac3cdad06897..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vsrc.rst
+++ /dev/null
@@ -1,21 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vsrc:
-
-vsrc
-====
-
-Interpolation parameter to read:
-
- ============ ===================================
- Syntax Description
- ============ ===================================
- p0 Parameter *P0*.
- p10 Parameter *P10*.
- p20 Parameter *P20*.
- ============ ===================================
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc0.rst b/llvm/docs/AMDGPU/gfx950_vsrc0.rst
deleted file mode 100644
index d17b0615538f7..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vsrc0.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vsrc0:
-
-vsrc0
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst b/llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst
deleted file mode 100644
index a15ad102091ec..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vsrc1_6802ce.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vsrc1_6802ce:
-
-vsrc1
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst b/llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst
deleted file mode 100644
index 3b89c6984f591..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vsrc1_fd235e.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vsrc1_fd235e:
-
-vsrc1
-=====
-
-Instruction input.
-
-*Size:* 2 dwords.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc2.rst b/llvm/docs/AMDGPU/gfx950_vsrc2.rst
deleted file mode 100644
index 56d4e0dc3ed1d..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vsrc2.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vsrc2:
-
-vsrc2
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx950_vsrc3.rst b/llvm/docs/AMDGPU/gfx950_vsrc3.rst
deleted file mode 100644
index 5c65b97287d6c..0000000000000
--- a/llvm/docs/AMDGPU/gfx950_vsrc3.rst
+++ /dev/null
@@ -1,17 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx950_vsrc3:
-
-vsrc3
-=====
-
-Instruction input.
-
-*Size:* 1 dword.
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
>From fa4b2c83ec83634ec174039f2d70074c76c02cf5 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Fri, 6 Mar 2026 15:06:01 -0800
Subject: [PATCH 3/3] [AMDGPU][MC] Allow nolds in some buffer_load instructions
Some pre-GFX11 buffer_load instructions have two variants: one
requires the lds modifier and one does not allow lds. For the latter
allow nolds to be used.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 1 +
llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s | 18 ++++++++++++++++++
llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s | 18 ++++++++++++++++++
llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s | 18 ++++++++++++++++++
llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s | 18 ++++++++++++++++++
6 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index fddb36133afb8..03fb2fb1740ff 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -10520,7 +10520,7 @@ ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,
case MCK_idxen:
return parseTokenOp("idxen", Operands);
case MCK_lds:
- return parseTokenOp("lds", Operands);
+ return parseNamedBit("lds", Operands, AMDGPUOperand::ImmTyLDS, true);
case MCK_offen:
return parseTokenOp("offen", Operands);
case MCK_off:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 2075e08b21f00..63297cd2a52d0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1252,6 +1252,7 @@ def Offset1 : NamedIntOperand<"offset1">;
}
def gds : NamedBitOperand<"gds", "GDS">;
+def lds : NamedBitOperand<"lds", "LDS", 1>;
def omod : CustomOperand<i32, 1, "OModSI">;
def omod0 : DefaultOperand<omod, 0>;
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
index 9f306fb9a9464..640bdfd28fc2f 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
@@ -1107,6 +1107,9 @@ buffer_gl1_inv
buffer_load_dword v255, off, s[8:11], s3 offset:4095
// GFX10: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_dword v255, off, s[8:11], s3 offset:4095 nolds
+// GFX10: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_dword v5, off, s[12:15], s3 offset:4095
// GFX10: buffer_load_dword v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x03,0x03]
@@ -1338,6 +1341,9 @@ buffer_load_format_d16_xyzw v[1:2], off, s[4:7], s1
buffer_load_format_x v255, off, s[8:11], s3 offset:4095
// GFX10: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095 nolds
+// GFX10: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_format_x v5, off, s[12:15], s3 offset:4095
// GFX10: buffer_load_format_x v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
@@ -1554,6 +1560,9 @@ buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
// GFX10: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 nolds
+// GFX10: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
// GFX10: buffer_load_sbyte v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
@@ -1608,6 +1617,9 @@ buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
buffer_load_sshort v255, off, s[8:11], s3 offset:4095
// GFX10: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095 nolds
+// GFX10: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sshort v5, off, s[12:15], s3 offset:4095
// GFX10: buffer_load_sshort v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
@@ -1662,6 +1674,9 @@ buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
// GFX10: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 nolds
+// GFX10: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
// GFX10: buffer_load_ubyte v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
@@ -1716,6 +1731,9 @@ buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
buffer_load_ushort v255, off, s[8:11], s3 offset:4095
// GFX10: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095 nolds
+// GFX10: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ushort v5, off, s[12:15], s3 offset:4095
// GFX10: buffer_load_ushort v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
index 7a1ec90c16b9b..639992cfbdbf9 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
@@ -3172,6 +3172,9 @@ buffer_atomic_xor_x2 v[254:255], off, s[12:15], s4 offset:4095
buffer_load_dword v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_dword v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_dword v5, off, s[100:103], s3 offset:4095
// CHECK: buffer_load_dword v5, off, s[100:103], s3 offset:4095 ; encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x19,0x03]
@@ -3568,6 +3571,9 @@ buffer_load_dwordx4 v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
buffer_load_format_x v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_format_x v5, off, s[100:103], s3 offset:4095
// CHECK: buffer_load_format_x v5, off, s[100:103], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x19,0x03]
@@ -3964,6 +3970,9 @@ buffer_load_format_xyzw v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sbyte v5, off, s[100:103], s3 offset:4095
// CHECK: buffer_load_sbyte v5, off, s[100:103], s3 offset:4095 ; encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x19,0x03]
@@ -4063,6 +4072,9 @@ buffer_load_sbyte v5, v[0:1], s[8:11], s3 addr64 offset:4095
buffer_load_sshort v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sshort v5, off, s[100:103], s3 offset:4095
// CHECK: buffer_load_sshort v5, off, s[100:103], s3 offset:4095 ; encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x19,0x03]
@@ -4162,6 +4174,9 @@ buffer_load_sshort v5, v[0:1], s[8:11], s3 addr64 offset:4095
buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ubyte v5, off, s[100:103], s3 offset:4095
// CHECK: buffer_load_ubyte v5, off, s[100:103], s3 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x19,0x03]
@@ -4261,6 +4276,9 @@ buffer_load_ubyte v5, v[0:1], s[8:11], s3 addr64 offset:4095
buffer_load_ushort v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ushort v5, off, s[100:103], s3 offset:4095
// CHECK: buffer_load_ushort v5, off, s[100:103], s3 offset:4095 ; encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x19,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
index 88a670a1166c6..4d42cdb9f5f30 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
@@ -2503,6 +2503,9 @@ buffer_load_dword off, s[8:11], s3 offset:4095 lds
buffer_load_dword v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_dword v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_dword v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_dword v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x03,0x03]
@@ -3274,6 +3277,9 @@ buffer_load_format_x off, s[8:11], s3 offset:4095 lds
buffer_load_format_x v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_format_x v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_format_x v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
@@ -3661,6 +3667,9 @@ buffer_load_sbyte off, s[8:11], s3 offset:4095 lds
buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_sbyte v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x03,0x03]
@@ -3760,6 +3769,9 @@ buffer_load_sshort off, s[8:11], s3 offset:4095 lds
buffer_load_sshort v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sshort v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_sshort v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x03,0x03]
@@ -3859,6 +3871,9 @@ buffer_load_ubyte off, s[8:11], s3 offset:4095 lds
buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_ubyte v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x03,0x03]
@@ -3958,6 +3973,9 @@ buffer_load_ushort off, s[8:11], s3 offset:4095 lds
buffer_load_ushort v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ushort v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_ushort v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x03,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
index c7c633bb2bc4f..571c64d4fe87c 100644
--- a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
@@ -2191,6 +2191,9 @@ buffer_load_dword off, s[8:11], s3 offset:4095 lds
buffer_load_dword v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_dword v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_dword v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_dword v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_dword v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x03,0x03]
@@ -2950,6 +2953,9 @@ buffer_load_format_x off, s[8:11], s3 offset:4095 lds
buffer_load_format_x v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_format_x v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_format_x v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_format_x v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
@@ -3289,6 +3295,9 @@ buffer_load_sbyte off, s[8:11], s3 offset:4095 lds
buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_sbyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_sbyte v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x03,0x03]
@@ -3712,6 +3721,9 @@ buffer_load_sshort off, s[8:11], s3 offset:4095 lds
buffer_load_sshort v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_sshort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_sshort v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_sshort v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x03,0x03]
@@ -3799,6 +3811,9 @@ buffer_load_ubyte off, s[8:11], s3 offset:4095 lds
buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_ubyte v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_ubyte v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x03,0x03]
@@ -4054,6 +4069,9 @@ buffer_load_ushort off, s[8:11], s3 offset:4095 lds
buffer_load_ushort v255, off, s[8:11], s3 offset:4095
// CHECK: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095 nolds
+// CHECK: buffer_load_ushort v255, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
+
buffer_load_ushort v5, off, s[12:15], s3 offset:4095
// CHECK: buffer_load_ushort v5, off, s[12:15], s3 offset:4095 ; encoding: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x03,0x03]
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