[llvm] [AArch64] Add partial reduce patterns for new fdot instructions (PR #184659)

[Paul Walker via llvm-commits]

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@@ -2031,6 +2038,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       // We can use SVE2p1 fdot to emulate the fixed-length variant.
       setPartialReduceMLAAction(ISD::PARTIAL_REDUCE_FMLA, MVT::v4f32,
                                 MVT::v8f16, Custom);
+      setPartialReduceMLAAction(ISD::PARTIAL_REDUCE_FMLA, MVT::v2f32,
+                                MVT::v4f16, Custom);
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paulwalker-arm wrote:

As has been explained before, this is a thing for SVE because we've yet to implement full support for strict fp. For this reason we have an SVE specific rule in place to not use "invisible lanes"  indiscriminately so that we don't cause problems for those who might be relying, potentially unknowingly, on the existing albeit immature level of support.  Whilst there are cases that may well be safe, it is just safer to have a blanket rule that can be walked back once we're on firmer ground.

https://github.com/llvm/llvm-project/pull/184659