[llvm] [AArch64] Add partial reduce patterns for new fdot instructions (PR #184659)

[David Green via llvm-commits]

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@@ -2031,6 +2038,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       // We can use SVE2p1 fdot to emulate the fixed-length variant.
       setPartialReduceMLAAction(ISD::PARTIAL_REDUCE_FMLA, MVT::v4f32,
                                 MVT::v8f16, Custom);
+      setPartialReduceMLAAction(ISD::PARTIAL_REDUCE_FMLA, MVT::v2f32,
+                                MVT::v4f16, Custom);
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davemgreen wrote:

> as it might introduce faulting behaviour for the inactive lanes if the runtime vector length > 128bits.

This isn't a thing. it sounds like a misunderstanding of how strictfp is treated in llvm.  There is not observable  "faulting" fp instructions outside of strict-fp.

https://github.com/llvm/llvm-project/pull/184659