[llvm] [HEXAGON] fp_to_uint conversion for v32f32 to v32i1 (PR #183248)

[Brian Cain via llvm-commits]

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@@ -434,6 +434,279 @@ SDValue HexagonTargetLowering::LowerCallResult(
   return Chain;
 }
 
+// Custom inserter for lowering PS_HVX_FPTU1_V32F32_TO_V32I1_Vec &
+// PS_HVX_FPTS1_V32F32_TO_V32I1_Vec..
+//
+// Converts the pseudo-instruction (dst: HvxQR, src: HvxVR) into a small CFG
+// with a counted loop that builds a 1-bit predicate vector where each lane is
+// set to 1 if the corresponding lane in SrcV is non-zero.
+//
+// CFG transformation:
+//   - Split the current block at  MI: MBB -> AfterBB (live-ins updated).
+//   - Create three blocks: HeaderBB (original MBB), BodyBB (loop body),
+//     ExitBB (loop exit).
+//   - Edges:
+//       HeaderBB -> BodyBB      (fallthrough)
+//       BodyBB   -> BodyBB      (backedge)
+//       BodyBB   -> ExitBB
+//       ExitBB   -> AfterBB
+//   - Erase the original pseudo (MI.eraseFromParent()) and return ExitBB.
+//
+// HeaderBB (initialization):
+//   - Scalar constants (A2_tfrsi):
+//       Rzero = 0, Rone = 1, Rmask = 0x01010101, Rcnt = 32, Rrot = 124
+//   - Build Vzero safely (no self-use before def):
+//       Vzero = V6_vxor  SrcV, SrcV
+//   - Compute zero-lane predicate:
+//       Qeq0  = V6_veqsf SrcV, Vzero            // float equality
+//   - Mask vector by predicate (bitplane source):
+//       V1    = V6_vandqrt Qeq0, Rmask          // Q-masked AND with scalar
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androm3da wrote:

`V6_vandnqrt` below?

https://github.com/llvm/llvm-project/pull/183248