[llvm] [AArch64] Update clmul tests after #184403 (PR #184611)

[Aiden Grossman via llvm-commits]

https://github.com/boomanaiden154 created https://github.com/llvm/llvm-project/pull/184611

This was likely a mid-air collision with #183282. Update the tests to match the current state of HEAD.

>From 31737792aeda57a63037c302e44d69879cf25905 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengrossman at google.com>
Date: Wed, 4 Mar 2026 14:05:08 +0000
Subject: [PATCH] [AArch64] Update clmul tests after #184403

This was likely a mid-air collision with #183282. Update the tests to
match the current state of HEAD.
---
 llvm/test/CodeGen/AArch64/clmul-fixed.ll | 20 ++++++++++----------
 llvm/test/CodeGen/AArch64/clmul.ll       | 18 +++++++++---------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/clmul-fixed.ll b/llvm/test/CodeGen/AArch64/clmul-fixed.ll
index 61081c3342889..6dbc0b4a70f37 100644
--- a/llvm/test/CodeGen/AArch64/clmul-fixed.ll
+++ b/llvm/test/CodeGen/AArch64/clmul-fixed.ll
@@ -1728,21 +1728,21 @@ define <1 x i128> @clmul_v1i128_neon(<1 x i128> %x, <1 x i128> %y) {
 ; CHECK-AES:       // %bb.0:
 ; CHECK-AES-NEXT:    rbit x8, x2
 ; CHECK-AES-NEXT:    rbit x9, x0
-; CHECK-AES-NEXT:    fmov d0, x2
-; CHECK-AES-NEXT:    fmov d1, x1
-; CHECK-AES-NEXT:    fmov d2, x3
+; CHECK-AES-NEXT:    fmov d0, x3
+; CHECK-AES-NEXT:    fmov d1, x0
+; CHECK-AES-NEXT:    fmov d2, x2
 ; CHECK-AES-NEXT:    fmov d3, x8
 ; CHECK-AES-NEXT:    fmov d4, x9
-; CHECK-AES-NEXT:    pmull v1.1q, v1.1d, v0.1d
+; CHECK-AES-NEXT:    pmull v0.1q, v1.1d, v0.1d
 ; CHECK-AES-NEXT:    pmull v3.1q, v4.1d, v3.1d
-; CHECK-AES-NEXT:    fmov d4, x0
-; CHECK-AES-NEXT:    pmull v2.1q, v4.1d, v2.1d
-; CHECK-AES-NEXT:    fmov x9, d1
+; CHECK-AES-NEXT:    fmov d4, x1
+; CHECK-AES-NEXT:    pmull v1.1q, v1.1d, v2.1d
+; CHECK-AES-NEXT:    pmull v4.1q, v4.1d, v2.1d
+; CHECK-AES-NEXT:    fmov x10, d0
 ; CHECK-AES-NEXT:    fmov x8, d3
-; CHECK-AES-NEXT:    pmull v0.1q, v4.1d, v0.1d
-; CHECK-AES-NEXT:    fmov x10, d2
+; CHECK-AES-NEXT:    fmov x0, d1
+; CHECK-AES-NEXT:    fmov x9, d4
 ; CHECK-AES-NEXT:    rbit x8, x8
-; CHECK-AES-NEXT:    fmov x0, d0
 ; CHECK-AES-NEXT:    eor x9, x10, x9
 ; CHECK-AES-NEXT:    eor x1, x9, x8, lsr #1
 ; CHECK-AES-NEXT:    ret
diff --git a/llvm/test/CodeGen/AArch64/clmul.ll b/llvm/test/CodeGen/AArch64/clmul.ll
index 7a94696711882..ee182100fdfd8 100644
--- a/llvm/test/CodeGen/AArch64/clmul.ll
+++ b/llvm/test/CodeGen/AArch64/clmul.ll
@@ -179,9 +179,9 @@ define i32 @clmul_i32(i32 %x, i32 %y) {
 ;
 ; CHECK-AES-LABEL: clmul_i32:
 ; CHECK-AES:       // %bb.0:
-; CHECK-AES-NEXT:    fmov s0, w1
-; CHECK-AES-NEXT:    fmov s1, w0
-; CHECK-AES-NEXT:    pmull v0.1q, v1.1d, v0.1d
+; CHECK-AES-NEXT:    fmov s0, w0
+; CHECK-AES-NEXT:    fmov s1, w1
+; CHECK-AES-NEXT:    pmull v0.1q, v0.1d, v1.1d
 ; CHECK-AES-NEXT:    fmov w0, s0
 ; CHECK-AES-NEXT:    ret
   %a = call i32 @llvm.clmul.i32(i32 %x, i32 %y)
@@ -573,9 +573,9 @@ define i32 @clmul_i32_zext(i16 %x, i16 %y) {
 ; CHECK-AES:       // %bb.0:
 ; CHECK-AES-NEXT:    and w8, w0, #0xffff
 ; CHECK-AES-NEXT:    and w9, w1, #0xffff
-; CHECK-AES-NEXT:    fmov s0, w9
-; CHECK-AES-NEXT:    fmov s1, w8
-; CHECK-AES-NEXT:    pmull v0.1q, v1.1d, v0.1d
+; CHECK-AES-NEXT:    fmov s0, w8
+; CHECK-AES-NEXT:    fmov s1, w9
+; CHECK-AES-NEXT:    pmull v0.1q, v0.1d, v1.1d
 ; CHECK-AES-NEXT:    fmov w0, s0
 ; CHECK-AES-NEXT:    ret
   %zextx = zext i16 %x to i32
@@ -689,9 +689,9 @@ define i64 @clmul_i64_zext(i32 %x, i32 %y) {
 ; CHECK-AES:       // %bb.0:
 ; CHECK-AES-NEXT:    mov w8, w0
 ; CHECK-AES-NEXT:    mov w9, w1
-; CHECK-AES-NEXT:    fmov d0, x9
-; CHECK-AES-NEXT:    fmov d1, x8
-; CHECK-AES-NEXT:    pmull v0.1q, v1.1d, v0.1d
+; CHECK-AES-NEXT:    fmov d0, x8
+; CHECK-AES-NEXT:    fmov d1, x9
+; CHECK-AES-NEXT:    pmull v0.1q, v0.1d, v1.1d
 ; CHECK-AES-NEXT:    fmov x0, d0
 ; CHECK-AES-NEXT:    ret
   %zextx = zext i32 %x to i64