[llvm] [RISCV] Add findCommutedOpIndices support for Zvabd (PR #184602)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/184602

None

>From 8b3a725f22a0d2508c1ab7a4a9fc23e2e40bc209 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 4 Mar 2026 20:41:34 +0800
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
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Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6ddd058d8e2a8..e6fbd5c182ee8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4170,6 +4170,10 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   case CASE_RVV_OPCODE_WIDEN(VWMULU_VV):
   case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
   case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
+  case CASE_RVV_OPCODE(VABD_VV):
+  case CASE_RVV_OPCODE(VABDU_VV):
+  case CASE_RVV_OPCODE_WIDEN(VWABDA_VV):
+  case CASE_RVV_OPCODE_WIDEN(VWABDAU_VV):
   case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
   case CASE_RVV_OPCODE(VSADD_VV):
   case CASE_RVV_OPCODE(VSADDU_VV):