[llvm] [WebAssembly][FastISel] Omit redundant AND for zext of i8/i16 loads (PR #182240)

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Wed Mar 4 00:49:22 PST 2026

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ParkHanbum wrote:

this PR will replaced with https://github.com/llvm/llvm-project/pull/183743

https://github.com/llvm/llvm-project/pull/182240

Previous message: [llvm] [RISCV] Add register overlap checks to the assembler for vector indexed segment load (PR #184569)
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