[llvm] [RISCV] Combine unaligned scalar ld -> aligned vector ld (PR #183336)

Ramkumar Ramachandra via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 3 12:57:00 PST 2026


================
@@ -198,12 +198,12 @@ define <2 x i64> @mgather_v2i64_align4(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %
 ; RV64-SLOW-NEXT:    andi a1, a0, 1
 ; RV64-SLOW-NEXT:    beqz a1, .LBB5_2
 ; RV64-SLOW-NEXT:  # %bb.1: # %cond.load
-; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m8, tu, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; RV64-SLOW-NEXT:    vmv.x.s a1, v8
-; RV64-SLOW-NEXT:    lw a2, 4(a1)
-; RV64-SLOW-NEXT:    lwu a1, 0(a1)
-; RV64-SLOW-NEXT:    slli a2, a2, 32
-; RV64-SLOW-NEXT:    or a1, a2, a1
+; RV64-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT:    vle32.v v10, (a1)
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
+; RV64-SLOW-NEXT:    vmv.x.s a1, v10
 ; RV64-SLOW-NEXT:    vmv.s.x v9, a1
----------------
artagnon wrote:

This is the DAG:

```
SelectionDAG has 22 nodes:
  t0: ch,glue = EntryToken
          t8: v2i64,ch = CopyFromReg t0, Register:v2i64 %9
        t15: nxv1i64 = insert_subvector undef:nxv1i64, t8, Constant:i64<0>
                      t2: v2i64,ch = CopyFromReg t0, Register:v2i64 %8
                    t27: nxv1i64 = insert_subvector undef:nxv1i64, t2, Constant:i64<0>
                  t28: i64 = RISCVISD::VMV_X_S t27
                t24: nxv1i32,ch = llvm.riscv.vle<(load (s64) from %ir.Ptr0, align 4)> t0, TargetConstant:i64<12426>, undef:nxv1i32, t28, Constant:i64<2>
              t25: v2i32 = extract_subvector t24, Constant:i64<0>
            t20: v1i64 = bitcast t25
          t29: nxv1i64 = insert_subvector undef:nxv1i64, t20, Constant:i64<0>
        t30: i64 = RISCVISD::VMV_X_S t29
      t18: nxv1i64 = RISCVISD::VMV_S_X_VL t15, t30, Constant:i64<2>
    t19: v2i64 = extract_subvector t18, Constant:i64<0>
  t11: ch = CopyToReg t0, Register:v2i64 %1, t19
```

... and we're failing Passthru.isUndef() to fold here:

```cpp
  case RISCVISD::VMV_S_X_VL: {
    // ...
    if (Scalar.getOpcode() == RISCVISD::VMV_X_S && Passthru.isUndef() &&
        Scalar.getOperand(0).getValueType() == N->getValueType(0))
      return Scalar.getOperand(0);
```

https://github.com/llvm/llvm-project/pull/183336


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