[llvm] [RISCV] Combine unaligned scalar ld -> aligned vector ld (PR #183336)

[Ramkumar Ramachandra via llvm-commits]

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@@ -198,12 +198,12 @@ define <2 x i64> @mgather_v2i64_align4(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> %
 ; RV64-SLOW-NEXT:    andi a1, a0, 1
 ; RV64-SLOW-NEXT:    beqz a1, .LBB5_2
 ; RV64-SLOW-NEXT:  # %bb.1: # %cond.load
-; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m8, tu, ma
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
 ; RV64-SLOW-NEXT:    vmv.x.s a1, v8
-; RV64-SLOW-NEXT:    lw a2, 4(a1)
-; RV64-SLOW-NEXT:    lwu a1, 0(a1)
-; RV64-SLOW-NEXT:    slli a2, a2, 32
-; RV64-SLOW-NEXT:    or a1, a2, a1
+; RV64-SLOW-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; RV64-SLOW-NEXT:    vle32.v v10, (a1)
+; RV64-SLOW-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
+; RV64-SLOW-NEXT:    vmv.x.s a1, v10
 ; RV64-SLOW-NEXT:    vmv.s.x v9, a1
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artagnon wrote:

I have the following fold implemented trivially in RISC-V's InstCombine; let me know if you want me to post it for review first, before we can go ahead with this patch:

```llvm
define <vscale x 1 x i8> @trivial_constfold(<vscale x 1 x i8> %v, i64 %vl) {
; CHECK-LABEL: define <vscale x 1 x i8> @trivial_constfold(
; CHECK-SAME: <vscale x 1 x i8> [[V:%.*]], i64 [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    ret <vscale x 1 x i8> [[V]]
;
  %a = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> %v)
  %b = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8> %v, i8 %a, i64 %vl)
  ret <vscale x 1 x i8> %b
}
```

https://github.com/llvm/llvm-project/pull/183336