[llvm] [AMDGPU] Implement LSR cost model for GFX9+ (PR #184138)

[via llvm-commits]

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@@ -0,0 +1,37 @@
+; RUN: llc -O3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
+
+; Reduced from rocrand's threefry2x32_20 kernel.
+; The AMDGPU LSR cost model should avoid creating a redundant VGPR induction
+; variable when the loop already has a vector IV incremented by a uniform
+; (SGPR) stride. Without the cost model fix, LSR introduces a second v_add
+; in the loop body, wasting a VGPR and a VALU slot every iteration.
+
+declare i32 @llvm.amdgcn.workitem.id.x() #0
+
+; CHECK-LABEL: {{^}}lsr_vector_iv_cost:
+; The loop must contain exactly one VALU add — the single vector IV update.
+; A second v_add_u32 here would mean LSR created a redundant IV.
+; CHECK:      {{^}}.LBB0_1:
+; CHECK:      v_add_u32
+; CHECK-NOT:  v_add_u32
+; CHECK:      s_cbranch
+define amdgpu_kernel void @lsr_vector_iv_cost(<2 x i32> %arg0, i32 %stride) {
+entry:
+  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
+  br label %loop
+
+loop:
+  %iv.pn = phi i32 [ 0, %entry ], [ %or, %loop ]
+  %iv.vec = phi i32 [ %tid, %entry ], [ %sum1, %loop ]
+  %sum1 = add i32 %iv.vec, %stride
+  %elt = extractelement <2 x i32> %arg0, i64 0
+  %sum2 = add i32 %sum1, %elt
+  %xor = xor i32 1, %sum2
+  %sum3 = add i32 %sum2, %xor
+  %sum4 = add i32 %sum3, %elt
+  %or = or i32 %sum4, %stride
+  %shr = lshr i32 %iv.pn, 1
+  br label %loop
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michaelselehov wrote:

Fixed — added an exit condition (icmp ult) and a store in the exit block so the loop has observable side effects and won't be eliminated by future DCE/loop-deletion passes.

https://github.com/llvm/llvm-project/pull/184138