[llvm] [AArch64][ISel] Use vector register for scalar CLMUL (PR #183282)

[David Green via llvm-commits]

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@@ -8062,6 +8057,38 @@ SDValue AArch64TargetLowering::LowerFMA(SDValue Op, SelectionDAG &DAG) const {
   return convertFromScalableVector(DAG, VT, ScalableRes);
 }
 
+static SDValue LowerCLMUL(SDValue Op, SelectionDAG &DAG) {
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), VT, 64 / VT.getSizeInBits());
+  EVT CLMULTy = VT == MVT::i8 ? MVT::v8i8 : MVT::v1i64;
+  EVT ExtractTy = VT == MVT::i64 ? MVT::i64 : MVT::i32;
+  EVT ExtractVecTy = VT == MVT::i64 ? MVT::v1i64 : MVT::v2i32;
+
+  SDValue Op0 = Op.getOperand(0);
+  SDValue Op1 = Op.getOperand(1);
+  if (Op0.getOpcode() == ISD::TRUNCATE)
+    Op0 = Op0.getOperand(0);
+  if (Op1.getOpcode() == ISD::TRUNCATE)
+    Op1 = Op1.getOperand(0);
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davemgreen wrote:

There is a chance it might when types are legal, as all types then need to be i32/i64 even  if inserting into a v8i8 vector. But if we have a i8 input already then it should be OK to produce one with an i8 and let the SCALAR_TO_VECTOR legalize I think.

https://github.com/llvm/llvm-project/pull/183282