[llvm] [AArch64][ISel] Use vector register for scalar CLMUL (PR #183282)

[Matthew Devereau via llvm-commits]

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@@ -8062,6 +8057,38 @@ SDValue AArch64TargetLowering::LowerFMA(SDValue Op, SelectionDAG &DAG) const {
   return convertFromScalableVector(DAG, VT, ScalableRes);
 }
 
+static SDValue LowerCLMUL(SDValue Op, SelectionDAG &DAG) {
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), VT, 64 / VT.getSizeInBits());
+  EVT CLMULTy = VT == MVT::i8 ? MVT::v8i8 : MVT::v1i64;
+  EVT ExtractTy = VT == MVT::i64 ? MVT::i64 : MVT::i32;
+  EVT ExtractVecTy = VT == MVT::i64 ? MVT::v1i64 : MVT::v2i32;
+
+  SDValue Op0 = Op.getOperand(0);
+  SDValue Op1 = Op.getOperand(1);
+  if (Op0.getOpcode() == ISD::TRUNCATE)
+    Op0 = Op0.getOperand(0);
+  if (Op1.getOpcode() == ISD::TRUNCATE)
+    Op1 = Op1.getOperand(0);
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MDevereau wrote:

For some reason something I saw when working on this initially made me convinced ISD::SCALAR_TO_VECTOR had to take an i32/i64 scalar, but it does not upon further inspection. You're right that this isn't necessary, so I've removed them.

https://github.com/llvm/llvm-project/pull/183282