[llvm] [RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (PR #182598)

[Craig Topper via llvm-commits]

topperc wrote:

> > LGTM - is the hope here that this might be more compressible than the `bexti`?
> 
> Yeah. Does Xqci have any compressible bit test instructions that cover this range?

Not shown here. Without Zbs we generate this before this patch. I guess I need to add yet more RUN lines.

single_bit4:                            # @single_bit4
        .cfi_startproc
# %bb.0:                                # %entry
        slli    a1, a0, 53
        srli    a1, a1, 63
        czero.nez       a0, a0, a1
        ret

https://github.com/llvm/llvm-project/pull/182598