[llvm] [RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (PR #182598)

[Craig Topper via llvm-commits]

topperc wrote:

> LGTM - is the hope here that this might be more compressible than the `bexti`?

Yeah. Does Xqci have any compressible bit test instructions that cover this range?

https://github.com/llvm/llvm-project/pull/182598