[llvm] [X86] i512 shift expansion on AVX512 targets (PR #180432)

[Simon Pilgrim via llvm-commits]

================
@@ -34354,6 +34333,83 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
     Results.push_back(DAG.getBitcast(VT, Res));
     return;
   }
+  case ISD::SRA:
+  case ISD::SRL:
+  case ISD::SHL: {
+    SDValue ShiftVal = N->getOperand(0);
+    SDValue ShiftAmt = N->getOperand(1);
+    SDLoc DL(N);
+    EVT VT = N->getValueType(0);
+    assert(VT == MVT::i512 && "Unexpected VT!");
+    assert(Subtarget.useAVX512Regs() && "AVX512 required");
+
+    EVT VecVT = MVT::v8i64;
+    SDValue ShiftValVec = DAG.getBitcast(VecVT, ShiftVal);
+    SDValue ShiftAmtExt = DAG.getZExtOrTrunc(ShiftAmt, DL, MVT::i32);
+
+    // Complete Lanes to shift
+    SDValue LaneShift = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftAmtExt,
+                                    DAG.getConstant(6, DL, MVT::i32));
+
+    // Remaining bits to shift
+    SDValue BitShift = DAG.getNode(ISD::UREM, DL, MVT::i32, ShiftAmtExt,
+                                   DAG.getConstant(64, DL, MVT::i32));
+
+    SDValue BitShift64 = DAG.getZExtOrTrunc(BitShift, DL, MVT::i64);
+    SDValue BitShiftV = DAG.getSplatBuildVector(VecVT, DL, BitShift64);
+
+    SDValue MaskShift =
+        DAG.getNode(ISD::SHL, DL, MVT::i8, DAG.getConstant(0xFF, DL, MVT::i8),
+                    DAG.getZExtOrTrunc(LaneShift, DL, MVT::i8));
+
+    SDValue ZeroV = DAG.getConstant(0, DL, VecVT);
+
+    SDValue Lo, Hi, Res;
+    bool IsShiftLeft = Opc == ISD::SHL;
+
+    switch (Opc) {
+    case ISD::SHL: {
+      Lo =
+          DAG.getNode(X86ISD::EXPAND, DL, VecVT, ShiftValVec, MaskShift, ZeroV);
+
+      Hi = DAG.getNode(X86ISD::PALIGNR, DL, VecVT, Lo, ZeroV,
+                       DAG.getConstant(7 * 8, DL, MVT::i8));
+      break;
+    }
+    case ISD::SRL: {
+      Hi = DAG.getNode(X86ISD::COMPRESS, DL, VecVT, ShiftValVec, MaskShift,
----------------
RKSimon wrote:

The argument order is CmpVec, PassThru, MaskPredicate

https://github.com/llvm/llvm-project/pull/180432