[llvm] [X86] i512 shift expansion on AVX512 targets (PR #180432)

[Aryan Kadole via llvm-commits]

ak1932 wrote:

> @ak1932 ping - any luck?

Sorry, I had my university exams last week. I had assumed I would be able to solve this issue before the exams, but could not. I tried llc --debug and found out that that the EXPAND and COMPRESS nodes required the operand order as `(src: v8i64, a: v8164, mask: i8)` when the [intel intrinsics guide](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512&text=expand&ig_expand=2859) which I was using as reference has `(src: v8i64, mask: i8, a: v8164)`. This was where my build was crashing 😅.
Why would this be the case that operand order is different in llvm and for intel?

https://github.com/llvm/llvm-project/pull/180432