[llvm] [RISCV] Ensure false dominates in vmerge peephole (PR #181664)

[Luke Lau via llvm-commits]

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@@ -558,20 +559,34 @@ static bool isSafeToMove(const MachineInstr &From, const MachineInstr &To) {
   return From.isSafeToMove(SawStore);
 }
 
+/// Given \p A and \p B are in the same block, returns the instruction that
+/// comes first.
+static MachineBasicBlock::iterator first(MachineBasicBlock::iterator A,
+                                         MachineBasicBlock::iterator B) {
+  assert(A->getParent() == B->getParent());
+  MachineBasicBlock::iterator I = A->getParent()->begin();
+  for (; &*I != A && &*I != B; ++I)
+    ;
+  return I;
+}
+
+/// Given \p A and \p B are in the same block, returns the instruction that
+/// comes last.
+static MachineBasicBlock::iterator last(MachineBasicBlock::iterator A,
+                                        MachineBasicBlock::iterator B) {
+  return first(A, B) == A ? B : A;
+}
+
 /// Given A and B are in the same MBB, returns true if A comes before B.
-static bool dominates(MachineBasicBlock::const_iterator A,
-                      MachineBasicBlock::const_iterator B) {
+static bool dominates(MachineBasicBlock::iterator A,
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lukel97 wrote:

This part of the diff went away in 20c63d8d7ba4

https://github.com/llvm/llvm-project/pull/181664