[llvm] [RISCV] Ensure false dominates in vmerge peephole (PR #181664)

[Luke Lau via llvm-commits]

================
@@ -832,10 +851,14 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
   assert(RISCVII::hasVecPolicyOp(True.getDesc().TSFlags) &&
          "Foldable unmasked pseudo should have a policy op already");
 
-  // Make sure the mask dominates True and its copies, otherwise move down True
-  // so it does. VL will always dominate since if it's a register they need to
-  // be the same.
-  if (!ensureDominates(MaskOp, True))
+  // Make sure both mask and false dominate True and its copies, otherwise move
+  // down True so it does. VL will always dominate since if it's a register they
+  // need to be the same.
+  MachineInstr *False = MRI->getUniqueVRegDef(FalseReg);
+  MachineInstr *LastDef = Mask;
+  if (False && False->getParent() == Mask->getParent())
+    LastDef = &*last(LastDef, False);
+  if (!ensureDominates(LastDef, True))
----------------
lukel97 wrote:

I think we can use get the False MachineOperand, thanks for suggesting that. I was able to remove the overload of ensureDominates in 20c63d8d7ba4 so it should be a smaller diff now

https://github.com/llvm/llvm-project/pull/181664