[llvm] [AArch64] Codegen for AArch64 Return Address Signing Hardening (PR #176187)

[Victor Campos via llvm-commits]

================
@@ -10013,6 +10013,23 @@ AArch64InstrInfo::getOutliningCandidateInfo(
                                    ->getInfo<AArch64FunctionInfo>()
                                    ->getSignReturnAddressCondition();
   if (RASignCondition != SignReturnAddress::None) {
+    // Candidates that have Return Address Signing Hardening enabled are
+    // discarded.
+    //
+    // In its current form, the machine outliner does not preserve X16/X17
----------------
vhscampos wrote:

Thanks for the comment.

The machine outliner still has this bug of not preserving X16 or X17.

So the point of this code comment is that outlining and pac-ret hardening are not compatible because there's an odd chance that the RegScavenger will pick X16 or X17 as the temporary register. To the best of my knowledge, if any other register is picked, it would be ok. However it would fall apart if it was X16/X17.

I can try and reword the comment if you'd like.

https://github.com/llvm/llvm-project/pull/176187