[llvm] [AArch64] Codegen for AArch64 Return Address Signing Hardening (PR #176187)

[Victor Campos via llvm-commits]

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@@ -276,5 +285,86 @@ bool AArch64PointerAuth::runOnMachineFunction(MachineFunction &MF) {
     Modified = true;
   }
 
+  Modified |= emitSignReturnAddressHardening(MF);
+
+  return Modified;
+}
+
+bool AArch64PointerAuth::emitSignReturnAddressHardening(MachineFunction &MF) {
+  const auto *FI = MF.getInfo<AArch64FunctionInfo>();
+  assert(FI && "FI can't be null");
+  if (!FI->shouldSignReturnAddress(MF) || !FI->shouldHardenSignReturnAddress())
+    return false;
+  assert(Subtarget && "Subtarget must be initialized");
+
+  RegScavenger RS;
+  bool Modified = false;
+  for (MachineBasicBlock &MBB : MF) {
+    if (!MBB.isReturnBlock())
+      continue;
+
+    MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
+
+    if (MBBI == MBB.end() || MBBI->getOpcode() != AArch64::RET)
+      continue;
+
+    RS.enterBasicBlockEnd(*MBBI->getParent());
+    Register XReg = RS.scavengeRegisterBackwards(
+        AArch64::GPR64RegClass, MBBI,
+        /*RestoreAfter=*/false, /*SPAdj=*/0, /*AllowSpill=*/false);
+    if (XReg == AArch64::NoRegister)
+      // Couldn't find a free register to use for the hardening. Skip.
----------------
vhscampos wrote:

I managed to create an MIR test to exercise this code path. It's very artificial, but gets the job done.

https://github.com/llvm/llvm-project/pull/176187