[llvm] [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (PR #180472)

[via llvm-commits]

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@@ -18361,9 +18361,17 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
     return Zeroable[M.index()] || (M.value() == (int)M.index());
   });
   if (IsBlendWithZero) {
-    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
-    SDValue BlendMask = DAG.getConstant(~Zeroable, DL, IntVT);
-    return DAG.getNode(ISD::AND, DL, VT, V1, DAG.getBitcast(VT, BlendMask));
+    const unsigned Width = std::max<unsigned>(NumElts, 8u);
+    MVT IntVT = MVT::getIntegerVT(Width);
+
+    APInt MaskVlaue = (~Zeroable).zextOrTrunc(Width);
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woruyu wrote:

Done!

https://github.com/llvm/llvm-project/pull/180472