[llvm] [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (PR #180472)

[via llvm-commits]

https://github.com/woruyu updated https://github.com/llvm/llvm-project/pull/180472

>From 8ad9294bf64b4b1eb6fe5a883d055d8df6eac926 Mon Sep 17 00:00:00 2001
From: woruyu <1214539920 at qq.com>
Date: Mon, 9 Feb 2026 14:42:26 +0800
Subject: [PATCH 1/3] [X86] Fix lower1BitShuffle blend-with-zero shuffles to
 AND mask

---
 llvm/lib/Target/X86/X86ISelLowering.cpp   | 12 +++++++++---
 llvm/test/CodeGen/X86/avx512bwvl-arith.ll | 15 +++++++++++++++
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8d9359b6fc3d2..ac7db1eaea597 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18361,9 +18361,15 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
     return Zeroable[M.index()] || (M.value() == (int)M.index());
   });
   if (IsBlendWithZero) {
-    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
-    SDValue BlendMask = DAG.getConstant(~Zeroable, DL, IntVT);
-    return DAG.getNode(ISD::AND, DL, VT, V1, DAG.getBitcast(VT, BlendMask));
+    SmallVector<SDValue, 32> MaskElts;
+    MaskElts.reserve(NumElts);
+
+    for (int I = 0; I != NumElts; ++I) {
+      MaskElts.push_back(DAG.getConstant(Zeroable[I] ? 0 : 1, DL, MVT::i8));
+    }
+
+    SDValue MaskVec = DAG.getBuildVector(VT, DL, MaskElts);
+    return DAG.getNode(ISD::AND, DL, VT, V1, MaskVec);
   }
 
   MVT ExtVT;
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
index decab7b485c4d..f62f02d44bfeb 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
@@ -250,3 +250,18 @@ define i16 @PR90356(<16 x i1> %a) {
   %2 = bitcast <16 x i1> %1 to i16
   ret i16 %2
 }
+
+define <4 x i1> @ISSUE180426(<4 x i1> %0) {
+; CHECK-LABEL: ISSUE180426:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT:    movb $5, %al
+; CHECK-NEXT:    kmovd %eax, %k1
+; CHECK-NEXT:    vptestmd %xmm0, %xmm0, %k1 {%k1}
+; CHECK-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovdqa32 %xmm0, %xmm0 {%k1} {z}
+; CHECK-NEXT:    retq
+entry:
+  %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  ret <4 x i1> %1
+}

>From ad3a8bd0a7abe42654405a9af122dfa85314b122 Mon Sep 17 00:00:00 2001
From: woruyu <1214539920 at qq.com>
Date: Tue, 10 Feb 2026 11:02:27 +0800
Subject: [PATCH 2/3] fix: review

---
 llvm/lib/Target/X86/X86ISelLowering.cpp   | 14 ++++++++------
 llvm/test/CodeGen/X86/avx512bwvl-arith.ll | 11 +++++------
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ac7db1eaea597..133a995b60487 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18361,14 +18361,16 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
     return Zeroable[M.index()] || (M.value() == (int)M.index());
   });
   if (IsBlendWithZero) {
-    SmallVector<SDValue, 32> MaskElts;
-    MaskElts.reserve(NumElts);
+    const unsigned Width = std::max<unsigned>(NumElts, 8u);
+    MVT IntVT = MVT::getIntegerVT(Width);
 
-    for (int I = 0; I != NumElts; ++I) {
-      MaskElts.push_back(DAG.getConstant(Zeroable[I] ? 0 : 1, DL, MVT::i8));
-    }
+    APInt MaskVlaue = (~Zeroable).zextOrTrunc(Width);
+    SDValue MaskNode = DAG.getConstant(MaskVlaue, DL, IntVT);
+
+    MVT MaskVecVT = MVT::getVectorVT(MVT::i1, Width);
+    SDValue MaskVecNode = DAG.getBitcast(MaskVecVT, MaskNode);
 
-    SDValue MaskVec = DAG.getBuildVector(VT, DL, MaskElts);
+    SDValue MaskVec = DAG.getExtractSubvector(DL, VT, MaskVecNode, 0);
     return DAG.getNode(ISD::AND, DL, VT, V1, MaskVec);
   }
 
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
index f62f02d44bfeb..a7b93924e6f82 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
@@ -251,9 +251,9 @@ define i16 @PR90356(<16 x i1> %a) {
   ret i16 %2
 }
 
-define <4 x i1> @ISSUE180426(<4 x i1> %0) {
-; CHECK-LABEL: ISSUE180426:
-; CHECK:       # %bb.0: # %entry
+define <4 x i1> @PR180472(<4 x i1> %0) {
+; CHECK-LABEL: PR180472:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpslld $31, %xmm0, %xmm0
 ; CHECK-NEXT:    movb $5, %al
 ; CHECK-NEXT:    kmovd %eax, %k1
@@ -261,7 +261,6 @@ define <4 x i1> @ISSUE180426(<4 x i1> %0) {
 ; CHECK-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vmovdqa32 %xmm0, %xmm0 {%k1} {z}
 ; CHECK-NEXT:    retq
-entry:
-  %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
-  ret <4 x i1> %1
+  %x = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  ret <4 x i1> %x
 }

>From 62ecdb5942ea854737cfc4ff0d3b77632646f39e Mon Sep 17 00:00:00 2001
From: woruyu <1214539920 at qq.com>
Date: Tue, 10 Feb 2026 20:22:17 +0800
Subject: [PATCH 3/3] fix: spell error

---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 133a995b60487..9a21a50587797 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18364,8 +18364,8 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
     const unsigned Width = std::max<unsigned>(NumElts, 8u);
     MVT IntVT = MVT::getIntegerVT(Width);
 
-    APInt MaskVlaue = (~Zeroable).zextOrTrunc(Width);
-    SDValue MaskNode = DAG.getConstant(MaskVlaue, DL, IntVT);
+    APInt MaskValue = (~Zeroable).zextOrTrunc(Width);
+    SDValue MaskNode = DAG.getConstant(MaskValue, DL, IntVT);
 
     MVT MaskVecVT = MVT::getVectorVT(MVT::i1, Width);
     SDValue MaskVecNode = DAG.getBitcast(MaskVecVT, MaskNode);