[llvm] [DA] Fixing correctness issues in StrongSIV test (PR #178047)
Ehsan Amiri via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 9 10:49:25 PST 2026
https://github.com/amehsan updated https://github.com/llvm/llvm-project/pull/178047
>From f1dec402d5ea0ceefbd43cfce59f7f53778a6af0 Mon Sep 17 00:00:00 2001
From: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: Mon, 26 Jan 2026 12:40:48 -0500
Subject: [PATCH 1/6] [DA] Fixing correctness issues in StrongSIV test
Current implementation of Strong SIV test misses two checks. First it fails to
check that the AdddRecs considered are nsw. Also since we are checking for
signed overflow, all the numbers must be interpreted as signed. In particular
BTC must be proven to be non-negative. This check is also missing.
>From a vast number of experiments I have run, the proposed implementation
for checking non-negativity of BTC is good enough i.e. no opportunity is
missed because we fail to prove non-negativity of BTC.
---
llvm/lib/Analysis/DependenceAnalysis.cpp | 14 ++--
.../Analysis/DependenceAnalysis/BasePtrBug.ll | 2 +-
.../Analysis/DependenceAnalysis/DADelin.ll | 20 ++---
.../DependenceAnalysis/MIVCheckConst.ll | 7 +-
.../NonCanonicalizedSubscript.ll | 2 +-
.../DependenceAnalysis/Preliminary.ll | 10 +--
.../PreliminaryNoValidityCheckFixedSize.ll | 4 +-
.../SimpleSIVNoValidityCheck.ll | 12 +--
.../Analysis/DependenceAnalysis/StrongSIV.ll | 78 +++++++++---------
.../DependenceAnalysis/SymbolicRDIV.ll | 36 ++++-----
.../DependenceAnalysis/SymbolicSIV.ll | 80 +++++++++----------
.../DependenceAnalysis/WeakCrossingSIV.ll | 28 +++----
.../DependenceAnalysis/WeakZeroDstSIV.ll | 14 ++--
.../DependenceAnalysis/WeakZeroSrcSIV.ll | 14 ++--
.../becount-couldnotcompute.ll | 4 +-
.../DependenceAnalysis/non-monotonic.ll | 4 +-
.../LoopFusion/da_separate_loops.ll | 4 +-
17 files changed, 156 insertions(+), 177 deletions(-)
diff --git a/llvm/lib/Analysis/DependenceAnalysis.cpp b/llvm/lib/Analysis/DependenceAnalysis.cpp
index 51d0c32149330..204aa65a8fbc9 100644
--- a/llvm/lib/Analysis/DependenceAnalysis.cpp
+++ b/llvm/lib/Analysis/DependenceAnalysis.cpp
@@ -1364,9 +1364,8 @@ bool DependenceInfo::strongSIVtest(const SCEV *Coeff, const SCEV *SrcConst,
// check that |Delta| < iteration count
bool IsDeltaLarge = [&] {
const SCEV *UpperBound = collectUpperBound(CurSrcLoop, Delta->getType());
- if (!UpperBound)
+ if (!UpperBound || !SE->isKnownNonNegative(UpperBound))
return false;
-
LLVM_DEBUG(dbgs() << "\t UpperBound = " << *UpperBound);
LLVM_DEBUG(dbgs() << ", " << *UpperBound->getType() << "\n");
const SCEV *AbsDelta = absSCEVNoSignedOverflow(Delta, *SE);
@@ -2417,7 +2416,9 @@ bool DependenceInfo::testSIV(const SCEV *Src, const SCEV *Dst, unsigned &Level,
LLVM_DEBUG(dbgs() << " dst = " << *Dst << "\n");
const SCEVAddRecExpr *SrcAddRec = dyn_cast<SCEVAddRecExpr>(Src);
const SCEVAddRecExpr *DstAddRec = dyn_cast<SCEVAddRecExpr>(Dst);
- if (SrcAddRec && DstAddRec) {
+ bool SrcAnalyzable = SrcAddRec && SrcAddRec->hasNoSignedWrap();
+ bool DstAnalyzable = DstAddRec && DstAddRec->hasNoSignedWrap();
+ if (SrcAnalyzable && DstAnalyzable) {
const SCEV *SrcConst = SrcAddRec->getStart();
const SCEV *DstConst = DstAddRec->getStart();
const SCEV *SrcCoeff = SrcAddRec->getStepRecurrence(*SE);
@@ -2443,7 +2444,7 @@ bool DependenceInfo::testSIV(const SCEV *Src, const SCEV *Dst, unsigned &Level,
symbolicRDIVtest(SrcCoeff, DstCoeff, SrcConst, DstConst, CurSrcLoop,
CurDstLoop);
}
- if (SrcAddRec) {
+ if (SrcAnalyzable) {
const SCEV *SrcConst = SrcAddRec->getStart();
const SCEV *SrcCoeff = SrcAddRec->getStepRecurrence(*SE);
const SCEV *DstConst = Dst;
@@ -2453,7 +2454,7 @@ bool DependenceInfo::testSIV(const SCEV *Src, const SCEV *Dst, unsigned &Level,
CurSrcLoop, Level, Result) ||
gcdMIVtest(Src, Dst, Result);
}
- if (DstAddRec) {
+ if (DstAnalyzable) {
const SCEV *DstConst = DstAddRec->getStart();
const SCEV *DstCoeff = DstAddRec->getStepRecurrence(*SE);
const SCEV *SrcConst = Src;
@@ -2463,7 +2464,8 @@ bool DependenceInfo::testSIV(const SCEV *Src, const SCEV *Dst, unsigned &Level,
CurDstLoop, Level, Result) ||
gcdMIVtest(Src, Dst, Result);
}
- llvm_unreachable("SIV test expected at least one AddRec");
+ assert((SrcAddRec != nullptr || DstAddRec != nullptr) &&
+ "SIV test expected at least one AddRec");
return false;
}
diff --git a/llvm/test/Analysis/DependenceAnalysis/BasePtrBug.ll b/llvm/test/Analysis/DependenceAnalysis/BasePtrBug.ll
index 81e461a5e092d..49b015ee02e13 100644
--- a/llvm/test/Analysis/DependenceAnalysis/BasePtrBug.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/BasePtrBug.ll
@@ -22,7 +22,7 @@ define void @test1(ptr nocapture %A, ptr nocapture %B, i32 %N) #0 {
; CHECK-NEXT: Src: %0 = load i32, ptr %gep.0, align 4 --> Dst: store i32 %add, ptr %gep.B, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %1 = load i32, ptr %gep.1, align 4 --> Dst: %1 = load i32, ptr %gep.1, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %1 = load i32, ptr %gep.1, align 4 --> Dst: store i32 %add, ptr %gep.B, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %add, ptr %gep.B, align 4 --> Dst: store i32 %add, ptr %gep.B, align 4
diff --git a/llvm/test/Analysis/DependenceAnalysis/DADelin.ll b/llvm/test/Analysis/DependenceAnalysis/DADelin.ll
index 429e37de0a453..919a18b2fe976 100644
--- a/llvm/test/Analysis/DependenceAnalysis/DADelin.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/DADelin.ll
@@ -646,15 +646,11 @@ exit:
define void @coeff_may_negative(ptr %a, i32 %k) {
; CHECK-LABEL: 'coeff_may_negative'
; CHECK-NEXT: Src: store i8 42, ptr %idx.0, align 1 --> Dst: store i8 42, ptr %idx.0, align 1
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: %k ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i8 42, ptr %idx.0, align 1 --> Dst: store i8 42, ptr %idx.1, align 1
-; CHECK-NEXT: da analyze - output [*|<]!
+; CHECK-NEXT: da analyze - consistent output [*|<]!
; CHECK-NEXT: Src: store i8 42, ptr %idx.1, align 1 --> Dst: store i8 42, ptr %idx.1, align 1
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: %k ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
br label %loop
@@ -689,15 +685,11 @@ exit:
define void @coeff_positive(ptr %a, i32 %k) {
; CHECK-LABEL: 'coeff_positive'
; CHECK-NEXT: Src: store i8 42, ptr %idx.0, align 1 --> Dst: store i8 42, ptr %idx.0, align 1
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: %k ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i8 42, ptr %idx.0, align 1 --> Dst: store i8 42, ptr %idx.1, align 1
-; CHECK-NEXT: da analyze - output [*|<]!
+; CHECK-NEXT: da analyze - consistent output [*|<]!
; CHECK-NEXT: Src: store i8 42, ptr %idx.1, align 1 --> Dst: store i8 42, ptr %idx.1, align 1
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: %k ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
br label %loop
diff --git a/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll b/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
index d91a916d785c2..5e5302454bd6a 100644
--- a/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
@@ -39,18 +39,17 @@ define void @test(ptr %A, ptr %B, i1 %arg, i32 %n, i32 %m) align 2 {
; CHECK-NEXT: Src: %v1 = load i32, ptr %B, align 4 --> Dst: %v32 = load <32 x i32>, ptr %v30, align 128
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %v27 = load <32 x i32>, ptr %v25, align 256 --> Dst: %v27 = load <32 x i32>, ptr %v25, align 256
-; CHECK-NEXT: da analyze - consistent input [0 S S]!
+; CHECK-NEXT: da analyze - consistent input [* S S]!
; CHECK-NEXT: Runtime Assumptions:
; CHECK-NEXT: Equal predicate: (zext i7 (4 * (trunc i32 %v1 to i7) * (1 + (trunc i32 %n to i7))) to i32) == 0
; CHECK-NEXT: Equal predicate: (8 * (zext i4 (trunc i32 %v1 to i4) to i32))<nuw><nsw> == 0
-; CHECK-NEXT: Compare predicate: (8 * %v1) ne) 0
; CHECK-NEXT: Src: %v27 = load <32 x i32>, ptr %v25, align 256 --> Dst: %v32 = load <32 x i32>, ptr %v30, align 128
-; CHECK-NEXT: da analyze - input [* S S|<]!
+; CHECK-NEXT: da analyze - consistent input [* S S|<]!
; CHECK-NEXT: Runtime Assumptions:
; CHECK-NEXT: Equal predicate: (zext i7 (4 * (trunc i32 %v1 to i7) * (1 + (trunc i32 %n to i7))) to i32) == 0
; CHECK-NEXT: Equal predicate: (8 * (zext i4 (trunc i32 %v1 to i4) to i32))<nuw><nsw> == 0
; CHECK-NEXT: Src: %v32 = load <32 x i32>, ptr %v30, align 128 --> Dst: %v32 = load <32 x i32>, ptr %v30, align 128
-; CHECK-NEXT: da analyze - consistent input [0 S S]!
+; CHECK-NEXT: da analyze - consistent input [* S S]!
;
entry:
%v1 = load i32, ptr %B, align 4
diff --git a/llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll b/llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
index 0cee9aa90236a..1db0d4170ee09 100644
--- a/llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/NonCanonicalizedSubscript.ll
@@ -61,7 +61,7 @@ define void @coupled_miv_type_mismatch(i32 %n) {
; CHECK-NEXT: Src: %2 = load i32, ptr %arrayidx5, align 4 --> Dst: store i32 %add6, ptr %arrayidx10, align 4
; CHECK-NEXT: da analyze - anti [< >]!
; CHECK-NEXT: Src: store i32 %add6, ptr %arrayidx10, align 4 --> Dst: store i32 %add6, ptr %arrayidx10, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [0 *]!
;
entry:
br label %for.cond
diff --git a/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll b/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
index 8cb0e2ac770dc..de525d7c0cd2f 100644
--- a/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
@@ -448,7 +448,7 @@ define void @p4(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx5, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp sgt i64 %n, 0
@@ -501,7 +501,7 @@ define void @p5(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx5, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp sgt i64 %n, 0
@@ -727,11 +727,11 @@ entry:
define void @foo(ptr %s, i32 %size) nounwind uwtable ssp {
; CHECK-LABEL: 'foo'
; CHECK-NEXT: Src: %1 = load i32, ptr %0, align 4 --> Dst: %1 = load i32, ptr %0, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %1 = load i32, ptr %0, align 4 --> Dst: store i32 %1, ptr %i.02, align 4
-; CHECK-NEXT: da analyze - consistent anti [1]!
+; CHECK-NEXT: da analyze - consistent anti [*|<]!
; CHECK-NEXT: Src: store i32 %1, ptr %i.02, align 4 --> Dst: store i32 %1, ptr %i.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%idx.ext = zext i32 %size to i64
diff --git a/llvm/test/Analysis/DependenceAnalysis/PreliminaryNoValidityCheckFixedSize.ll b/llvm/test/Analysis/DependenceAnalysis/PreliminaryNoValidityCheckFixedSize.ll
index 8cd29e691a7ef..0cf2f8049f2a0 100644
--- a/llvm/test/Analysis/DependenceAnalysis/PreliminaryNoValidityCheckFixedSize.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/PreliminaryNoValidityCheckFixedSize.ll
@@ -20,11 +20,11 @@ define void @p2(i64 %n, ptr %A, ptr %B) nounwind uwtable ssp {
; CHECK-NEXT: Src: store i64 %i.011, ptr %arrayidx8, align 8 --> Dst: store i64 %i.011, ptr %arrayidx8, align 8
; CHECK-NEXT: da analyze - none!
; CHECK-NEXT: Src: store i64 %i.011, ptr %arrayidx8, align 8 --> Dst: %0 = load i64, ptr %arrayidx17, align 8
-; CHECK-NEXT: da analyze - flow [-3 -2] / assuming 1 loop level(s) fused: [-3 -2 -1]!
+; CHECK-NEXT: da analyze - flow [* *|<] / assuming 1 loop level(s) fused: [* * -1|<]!
; CHECK-NEXT: Src: store i64 %i.011, ptr %arrayidx8, align 8 --> Dst: store i64 %0, ptr %B.addr.24, align 8
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i64, ptr %arrayidx17, align 8 --> Dst: %0 = load i64, ptr %arrayidx17, align 8
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [* * 0]!
; CHECK-NEXT: Src: %0 = load i64, ptr %arrayidx17, align 8 --> Dst: store i64 %0, ptr %B.addr.24, align 8
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i64 %0, ptr %B.addr.24, align 8 --> Dst: store i64 %0, ptr %B.addr.24, align 8
diff --git a/llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll b/llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll
index 181a4494b036e..b04a206255f90 100644
--- a/llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll
@@ -78,11 +78,11 @@ for.end14: ; preds = %entry, %for.inc12
define void @t2(i32 signext %n, i32 signext %m, ptr %a) {
; CHECK-LABEL: 't2'
; CHECK-NEXT: Src: %21 = load i32, ptr %arrayidx28, align 4 --> Dst: %21 = load i32, ptr %arrayidx28, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [0 0 0 * 0]!
; CHECK-NEXT: Src: %21 = load i32, ptr %arrayidx28, align 4 --> Dst: store i32 %21, ptr %arrayidx38, align 4
-; CHECK-NEXT: da analyze - consistent anti [1 -2 0 -3 2]!
+; CHECK-NEXT: da analyze - consistent anti [1 -2 0 * 2]!
; CHECK-NEXT: Src: store i32 %21, ptr %arrayidx38, align 4 --> Dst: store i32 %21, ptr %arrayidx38, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [0 0 0 * 0]!
;
; LIN-LABEL: 't2'
; LIN-NEXT: Src: %21 = load i32, ptr %arrayidx28, align 4 --> Dst: %21 = load i32, ptr %arrayidx28, align 4
@@ -208,11 +208,11 @@ for.end50: ; preds = %entry, %for.inc48
define void @t3(i64 %n, i64 %m, i64 %lb, ptr %a) {
; CHECK-LABEL: 't3'
; CHECK-NEXT: Src: %2 = load i32, ptr %arrayidx6, align 4 --> Dst: %2 = load i32, ptr %arrayidx6, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [* *]!
; CHECK-NEXT: Src: %2 = load i32, ptr %arrayidx6, align 4 --> Dst: store i32 %2, ptr %arrayidx8, align 4
-; CHECK-NEXT: da analyze - anti [1 *]!
+; CHECK-NEXT: da analyze - consistent anti [* *|<]!
; CHECK-NEXT: Src: store i32 %2, ptr %arrayidx8, align 4 --> Dst: store i32 %2, ptr %arrayidx8, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [* *]!
;
; LIN-LABEL: 't3'
; LIN-NEXT: Src: %2 = load i32, ptr %arrayidx6, align 4 --> Dst: %2 = load i32, ptr %arrayidx6, align 4
diff --git a/llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll b/llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
index 0d73ada53ed18..bc026554f6ea2 100644
--- a/llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
@@ -114,17 +114,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @strong2(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'strong2'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - consistent flow [2]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -383,19 +383,33 @@ for.end: ; preds = %for.body
;; *B++ = A[i];
define void @strong8(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
-; CHECK-LABEL: 'strong8'
-; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
-; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
-; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
-; CHECK-NEXT: da analyze - confused!
-; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - none!
-; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
-; CHECK-NEXT: da analyze - confused!
-; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-ALL-LABEL: 'strong8'
+; CHECK-ALL-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
+; CHECK-ALL-NEXT: da analyze - consistent output [*]!
+; CHECK-ALL-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
+; CHECK-ALL-NEXT: da analyze - flow [*|<]!
+; CHECK-ALL-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
+; CHECK-ALL-NEXT: da analyze - confused!
+; CHECK-ALL-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
+; CHECK-ALL-NEXT: da analyze - none!
+; CHECK-ALL-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
+; CHECK-ALL-NEXT: da analyze - confused!
+; CHECK-ALL-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
+; CHECK-ALL-NEXT: da analyze - none!
+;
+; CHECK-STRONG-SIV-LABEL: 'strong8'
+; CHECK-STRONG-SIV-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
+; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [*]!
+; CHECK-STRONG-SIV-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
+; CHECK-STRONG-SIV-NEXT: da analyze - consistent flow [*|<]!
+; CHECK-STRONG-SIV-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
+; CHECK-STRONG-SIV-NEXT: da analyze - confused!
+; CHECK-STRONG-SIV-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
+; CHECK-STRONG-SIV-NEXT: da analyze - none!
+; CHECK-STRONG-SIV-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
+; CHECK-STRONG-SIV-NEXT: da analyze - confused!
+; CHECK-STRONG-SIV-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
+; CHECK-STRONG-SIV-NEXT: da analyze - none!
;
entry:
br label %for.body
@@ -427,17 +441,17 @@ for.end: ; preds = %for.body
define void @strong9(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'strong9'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -478,19 +492,13 @@ for.end: ; preds = %for.end.loopexit, %
define void @strong10(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'strong10'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - consistent flow [0|<]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - consistent input [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.01, align 4 --> Dst: store i32 %0, ptr %B.addr.01, align 4
@@ -528,13 +536,9 @@ for.end: ; preds = %for.body
;; A[i] = 0;
define void @strong11(ptr %A) nounwind uwtable ssp {
-; CHECK-ALL-LABEL: 'strong11'
-; CHECK-ALL-NEXT: Src: store i32 0, ptr %arrayidx, align 4 --> Dst: store i32 0, ptr %arrayidx, align 4
-; CHECK-ALL-NEXT: da analyze - none!
-;
-; CHECK-STRONG-SIV-LABEL: 'strong11'
-; CHECK-STRONG-SIV-NEXT: Src: store i32 0, ptr %arrayidx, align 4 --> Dst: store i32 0, ptr %arrayidx, align 4
-; CHECK-STRONG-SIV-NEXT: da analyze - consistent output [0 S]!
+; CHECK-LABEL: 'strong11'
+; CHECK-NEXT: Src: store i32 0, ptr %arrayidx, align 4 --> Dst: store i32 0, ptr %arrayidx, align 4
+; CHECK-NEXT: da analyze - consistent output [* S]!
;
entry:
br label %for.cond1.preheader
diff --git a/llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll b/llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
index e4fe577af1486..4e14f97240cf2 100644
--- a/llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
@@ -15,17 +15,17 @@ target triple = "x86_64-apple-macosx10.6.0"
define void @symbolicrdiv0(ptr %A, ptr %B, i64 %n1, i64 %n2) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicrdiv0'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx8, align 4
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx8, align 4 --> Dst: %0 = load i32, ptr %arrayidx8, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx8, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp4 = icmp eq i64 %n1, 0
@@ -84,17 +84,17 @@ for.end11: ; preds = %for.end11.loopexit,
define void @symbolicrdiv1(ptr %A, ptr %B, i64 %n1, i64 %n2) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicrdiv1'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx9, align 4
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx9, align 4 --> Dst: %0 = load i32, ptr %arrayidx9, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx9, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp4 = icmp eq i64 %n1, 0
@@ -155,17 +155,17 @@ for.end12: ; preds = %for.end12.loopexit,
define void @symbolicrdiv2(ptr %A, ptr %B, i64 %n1, i64 %n2) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicrdiv2'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp4 = icmp eq i64 %n1, 0
@@ -224,17 +224,17 @@ for.end10: ; preds = %for.end10.loopexit,
define void @symbolicrdiv3(ptr %A, ptr %B, i64 %n1, i64 %n2) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicrdiv3'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx6, align 4
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx6, align 4 --> Dst: %0 = load i32, ptr %arrayidx6, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx6, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp4 = icmp eq i64 %n1, 0
@@ -291,17 +291,17 @@ for.end9: ; preds = %for.end9.loopexit,
define void @symbolicrdiv4(ptr %A, ptr %B, i64 %n1, i64 %n2) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicrdiv4'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp4 = icmp eq i64 %n1, 0
@@ -359,17 +359,17 @@ for.end10: ; preds = %for.end10.loopexit,
define void @symbolicrdiv5(ptr %A, ptr %B, i64 %n1, i64 %n2) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicrdiv5'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp4 = icmp eq i64 %n1, 0
diff --git a/llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll b/llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
index 60bb065e4eaca..9907131aa891e 100644
--- a/llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
@@ -13,17 +13,17 @@ target triple = "x86_64-apple-macosx10.6.0"
define void @symbolicsiv0(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv0'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx4, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx4, align 4 --> Dst: %0 = load i32, ptr %arrayidx4, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx4, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -65,17 +65,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv1(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv1'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx5, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx5, align 4 --> Dst: %0 = load i32, ptr %arrayidx5, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx5, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -119,17 +119,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv2(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv2'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -171,17 +171,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv3(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv3'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -224,17 +224,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv4(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv4'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: %0 = load i32, ptr %arrayidx3, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx3, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -276,17 +276,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv5(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv5'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx4, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx4, align 4 --> Dst: %0 = load i32, ptr %arrayidx4, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx4, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -330,17 +330,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @weaktest(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'weaktest'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -381,21 +381,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv6(ptr %A, ptr %B, i64 %n, i64 %N, i64 %M) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv6'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (16 * %N) ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: %0 = load i32, ptr %arrayidx7, align 4
-; CHECK-NEXT: da analyze - consistent input [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (16 * %N) ne) 0
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx7, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -441,21 +437,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @symbolicsiv7(ptr %A, ptr %B, i64 %n, i64 %N, i64 %M) nounwind uwtable ssp {
; CHECK-LABEL: 'symbolicsiv7'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (8 * %N) ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %1 = load i32, ptr %arrayidx6, align 4
-; CHECK-NEXT: da analyze - flow [*|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %1, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %1 = load i32, ptr %arrayidx6, align 4 --> Dst: %1 = load i32, ptr %arrayidx6, align 4
-; CHECK-NEXT: da analyze - consistent input [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (8 * %N) ne) 0
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %1 = load i32, ptr %arrayidx6, align 4 --> Dst: store i32 %1, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %1, ptr %B.addr.02, align 4 --> Dst: store i32 %1, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
diff --git a/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll b/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
index c7accfd46a4d7..89e3032dcfc77 100644
--- a/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
@@ -14,21 +14,17 @@ target triple = "x86_64-apple-macosx10.6.0"
define void @weakcrossing0(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'weakcrossing0'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - flow [0|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - consistent input [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (-4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -70,17 +66,17 @@ for.end: ; preds = %for.end.loopexit, %
define void @weakcrossing1(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'weakcrossing1'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - flow [<>]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: %0 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -247,17 +243,17 @@ for.end: ; preds = %for.body
define void @weakcrossing5(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'weakcrossing5'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %1 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %1, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %1 = load i32, ptr %arrayidx2, align 4 --> Dst: %1 = load i32, ptr %arrayidx2, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %1 = load i32, ptr %arrayidx2, align 4 --> Dst: store i32 %1, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %1, ptr %B.addr.02, align 4 --> Dst: store i32 %1, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
diff --git a/llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll b/llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
index f8a045c425029..4e681fe22a748 100644
--- a/llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
@@ -90,11 +90,9 @@ for.end: ; preds = %for.body
define void @weakzerodst1(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'weakzerodst1'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - consistent output [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - flow [p<=|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
@@ -102,7 +100,7 @@ define void @weakzerodst1(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -310,9 +308,9 @@ for.end: ; preds = %for.body
define void @weakzerodst6(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-LABEL: 'weakzerodst6'
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
@@ -320,7 +318,7 @@ define void @weakzerodst6(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
diff --git a/llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll b/llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
index 4ed0abd8d98a9..0eb2b745cfc35 100644
--- a/llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
@@ -90,17 +90,15 @@ define void @weakzerosrc1(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
; CHECK-NEXT: da analyze - consistent output [S]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - flow [p=>|<]!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - consistent input [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 * %n) ne) 0
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
@@ -310,15 +308,15 @@ define void @weakzerosrc6(ptr %A, ptr %B, i64 %n) nounwind uwtable ssp {
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %conv, ptr %arrayidx, align 4
; CHECK-NEXT: da analyze - consistent output [S]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent flow [*|<]!
; CHECK-NEXT: Src: store i32 %conv, ptr %arrayidx, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: %0 = load i32, ptr %arrayidx1, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent input [*]!
; CHECK-NEXT: Src: %0 = load i32, ptr %arrayidx1, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
; CHECK-NEXT: da analyze - confused!
; CHECK-NEXT: Src: store i32 %0, ptr %B.addr.02, align 4 --> Dst: store i32 %0, ptr %B.addr.02, align 4
-; CHECK-NEXT: da analyze - none!
+; CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
%cmp1 = icmp eq i64 %n, 0
diff --git a/llvm/test/Analysis/DependenceAnalysis/becount-couldnotcompute.ll b/llvm/test/Analysis/DependenceAnalysis/becount-couldnotcompute.ll
index 1674badd4d6b9..5672e2c7b7c8b 100644
--- a/llvm/test/Analysis/DependenceAnalysis/becount-couldnotcompute.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/becount-couldnotcompute.ll
@@ -7,9 +7,7 @@
define void @test(i64 %conv, ptr %a) {
; CHECK-LABEL: 'test'
; CHECK-NEXT: Src: %ld = load i32, ptr %arrayidx12, align 4 --> Dst: %ld = load i32, ptr %arrayidx12, align 4
-; CHECK-NEXT: da analyze - consistent input [0]!
-; CHECK-NEXT: Runtime Assumptions:
-; CHECK-NEXT: Compare predicate: (4 + (4 * %conv)) ne) 0
+; CHECK-NEXT: da analyze - consistent input [*]!
;
entry:
%sub = add i64 %conv, 1
diff --git a/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll b/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll
index 6247336456d2c..28b76916fc521 100644
--- a/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll
+++ b/llvm/test/Analysis/DependenceAnalysis/non-monotonic.ll
@@ -46,9 +46,9 @@ define void @f(ptr %A) {
; DISABLE-CHECK-NEXT: Src: store i8 1, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.0, align 1
; DISABLE-CHECK-NEXT: da analyze - none!
; DISABLE-CHECK-NEXT: Src: store i8 1, ptr %idx.0, align 1 --> Dst: store i8 2, ptr %idx.1, align 1
-; DISABLE-CHECK-NEXT: da analyze - none!
+; DISABLE-CHECK-NEXT: da analyze - output [<>]!
; DISABLE-CHECK-NEXT: Src: store i8 2, ptr %idx.1, align 1 --> Dst: store i8 2, ptr %idx.1, align 1
-; DISABLE-CHECK-NEXT: da analyze - none!
+; DISABLE-CHECK-NEXT: da analyze - consistent output [*]!
;
entry:
br label %loop.header
diff --git a/llvm/test/Transforms/LoopFusion/da_separate_loops.ll b/llvm/test/Transforms/LoopFusion/da_separate_loops.ll
index 6359f48199290..a2f777adeb6f6 100644
--- a/llvm/test/Transforms/LoopFusion/da_separate_loops.ll
+++ b/llvm/test/Transforms/LoopFusion/da_separate_loops.ll
@@ -1,7 +1,7 @@
; REQUIRES: asserts
; RUN: opt -passes=loop-fusion -da-disable-delinearization-checks -disable-output -stats < %s 2>&1 | FileCheck -check-prefix=STAT %s
-; STAT: 2 loop-fusion - DA checks passed
+; STAT: 2 loop-fusion - Dependencies prevent fusion
; The two inner loops have no dependency and are allowed to be fused as in the
; outer loops, different levels are accessed to.
@@ -179,4 +179,4 @@ for.end26.loopexit: ; preds = %for.inc24
for.end26: ; preds = %for.end26.loopexit, %entry
ret void
-}
\ No newline at end of file
+}
>From 4a9298d36f77f61dcb8e592f09dffa17c72f6308 Mon Sep 17 00:00:00 2001
From: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: Tue, 27 Jan 2026 12:24:57 -0500
Subject: [PATCH 2/6] fixing unroll and jam testcase
---
.../LoopUnrollAndJam/dependencies.ll | 22 ++++++++++++-------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/test/Transforms/LoopUnrollAndJam/dependencies.ll b/llvm/test/Transforms/LoopUnrollAndJam/dependencies.ll
index 8dfe4b1dbf3af..1aecbf093403f 100644
--- a/llvm/test/Transforms/LoopUnrollAndJam/dependencies.ll
+++ b/llvm/test/Transforms/LoopUnrollAndJam/dependencies.ll
@@ -2,12 +2,14 @@
; RUN: opt -aa-pipeline=basic-aa -passes='loop-unroll-and-jam' -allow-unroll-and-jam -unroll-and-jam-count=4 < %s -S | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
-
; CHECK-LABEL: fore_aft_less
+; CHECK: %i = phi
+; CHECK-NOT: phi
; CHECK: %j = phi
-; CHECK: %j.1 = phi
-; CHECK: %j.2 = phi
-; CHECK: %j.3 = phi
+; CHECK-NOT: phi
+; CHECK: %sum = phi
+; CHECK-NOT: phi
+; CHECK: add.lcssa = phi
;
; fore_aft_less SHOULD be unroll-and-jammed (count=4) as it's safe.
; Memory accesses:
@@ -17,6 +19,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
; access different array elements, so unrolling the outer loop and jamming the
; inner loop is safe. The backward dependency (i-1) doesn't create conflicts
; between different unrolled iterations.
+; After PR#178047 we cannot prove safety of this transformation.
define void @fore_aft_less(ptr noalias nocapture %A, i32 %N, ptr noalias nocapture readonly %B) {
entry:
%cmp = icmp sgt i32 %N, 0
@@ -195,7 +198,6 @@ cleanup:
ret void
}
-
; CHECK-LABEL: fore_sub_eq
; CHECK: %j = phi
; CHECK: %j.1 = phi
@@ -293,10 +295,13 @@ cleanup:
; CHECK-LABEL: sub_aft_less
+; CHECK: %i = phi
+; CHECK-NOT: phi
; CHECK: %j = phi
-; CHECK: %j.1 = phi
-; CHECK: %j.2 = phi
-; CHECK: %j.3 = phi
+; CHECK-NOT: phi
+; CHECK: %sum = phi
+; CHECK-NOT: phi
+; CHECK: add.lcssa = phi
;
; sub_aft_less SHOULD be unroll-and-jammed (count=4) as it's safe.
; Memory accesses:
@@ -305,6 +310,7 @@ cleanup:
; No dependency conflict: The sub block writes A[i] and aft block writes A[i-1].
; These access different array elements, so unroll-and-jam is safe. The backward
; dependency pattern doesn't create conflicts between unrolled iterations.
+; After PR#178047 we cannot prove safety of this transformation.
define void @sub_aft_less(ptr noalias nocapture %A, i32 %N, ptr noalias nocapture readonly %B) {
entry:
%cmp = icmp sgt i32 %N, 0
>From 6e02529c3eb4ac6c8c66c36485e6fd342645bf56 Mon Sep 17 00:00:00 2001
From: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: Tue, 27 Jan 2026 15:50:24 -0500
Subject: [PATCH 3/6] fix DDG testcase
---
llvm/test/Analysis/DDG/basic-b.ll | 25 +++++++------------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/llvm/test/Analysis/DDG/basic-b.ll b/llvm/test/Analysis/DDG/basic-b.ll
index 66a6a83972406..3d7066d7502c1 100644
--- a/llvm/test/Analysis/DDG/basic-b.ll
+++ b/llvm/test/Analysis/DDG/basic-b.ll
@@ -38,40 +38,29 @@
; CHECK-NEXT: Instructions:
; CHECK-NEXT: %sub1 = add i64 %i.02, -1
; CHECK-NEXT: %arrayidx2 = getelementptr inbounds float, ptr %a, i64 %sub1
+; CHECK-NEXT: %1 = load float, ptr %arrayidx2, align 4
; CHECK-NEXT: Edges:
-; CHECK-NEXT: [def-use] to [[N8]]
+; CHECK-NEXT: [def-use] to [[N9:0x[0-9a-f]*]]
+; CHECK-NEXT: [memory] to [[N8]]
; CHECK: Node Address:[[N4]]:multi-instruction
; CHECK-NEXT: Instructions:
; CHECK-NEXT: %arrayidx = getelementptr inbounds float, ptr %b, i64 %i.02
; CHECK-NEXT: %0 = load float, ptr %arrayidx, align 4
; CHECK-NEXT: Edges:
-; CHECK-NEXT: [def-use] to [[N8]]
-
-; CHECK: Node Address:[[N8]]:pi-block
-; CHECK-NEXT: --- start of nodes in pi-block ---
-; CHECK: Node Address:[[N9:0x[0-9a-f]*]]:single-instruction
-; CHECK-NEXT: Instructions:
-; CHECK-NEXT: %1 = load float, ptr %arrayidx2, align 4
-; CHECK-NEXT: Edges:
-; CHECK-NEXT: [def-use] to [[N10:0x[0-9a-f]*]]
+; CHECK-NEXT: [def-use] to [[N9]]
-; CHECK: Node Address:[[N10]]:single-instruction
+; CHECK: Node Address:[[N9]]:single-instruction
; CHECK-NEXT: Instructions:
; CHECK-NEXT: %add = fadd float %0, %1
; CHECK-NEXT: Edges:
-; CHECK-NEXT: [def-use] to [[N11:0x[0-9a-f]*]]
+; CHECK-NEXT: [def-use] to [[N8:0x[0-9a-f]*]]
-; CHECK: Node Address:[[N11]]:single-instruction
+; CHECK: Node Address:[[N8]]:single-instruction
; CHECK-NEXT: Instructions:
; CHECK-NEXT: store float %add, ptr %arrayidx3, align 4
-; CHECK-NEXT: Edges:
-; CHECK-NEXT: [memory] to [[N9]]
-; CHECK-NEXT:--- end of nodes in pi-block ---
; CHECK-NEXT: Edges:none!
-
-
;; Loop-carried dependence requiring edge-reversal to expose a cycle
;; in the graph.
;; void test(unsigned long n, ptr restrict a, ptr restrict b) {
>From 324048670dc19489e8a20b9ea39ea80e6608f783 Mon Sep 17 00:00:00 2001
From: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: Sat, 7 Feb 2026 20:42:00 -0500
Subject: [PATCH 4/6] Fixing interchange testcases
---
.../reduction2mem-limitation.ll | 41 ++++---------------
.../LoopInterchange/reduction2mem.ll | 36 ++++++----------
2 files changed, 20 insertions(+), 57 deletions(-)
diff --git a/llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll b/llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
index d5303a576262d..ae2c066b3fa30 100644
--- a/llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
+++ b/llvm/test/Transforms/LoopInterchange/reduction2mem-limitation.ll
@@ -79,16 +79,10 @@ exit:
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedInnerReduction
-; CHECK-NEXT: Function: reduction_02
-; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only supports at most one reduction.
-; CHECK: --- !Missed
-; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedPHIInner
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: reduction_02
; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only inner loops with induction or reduction PHI nodes can be interchange currently.
+; CHECK-NEXT: - String: Cannot interchange loops due to dependences.
; IR-LABEL: @reduction_02(
; IR-NOT: split
@@ -144,16 +138,10 @@ exit:
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedInnerReduction
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: reduction_03
; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only supported when the reduction is used once in the outer loop.
-; CHECK: --- !Missed
-; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedPHIInner
-; CHECK-NEXT: Function: reduction_03
-; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only inner loops with induction or reduction PHI nodes can be interchange currently.
+; CHECK-NEXT: - String: Cannot interchange loops due to dependences.
; IR-LABEL: @reduction_03(
; IR-NOT: split
@@ -215,16 +203,10 @@ exit:
; CHECK-NEXT: - String: Only outer loops with induction or reduction PHI nodes can be interchanged currently.
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedInnerReduction
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: reduction_04
; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only supported when the loop is the innermost.
-; CHECK: --- !Missed
-; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedPHIInner
-; CHECK-NEXT: Function: reduction_04
-; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only inner loops with induction or reduction PHI nodes can be interchange currently.
+; CHECK-NEXT: - String: Cannot interchange loops due to dependences.
; IR-LABEL: @reduction_04(
; IR-NOT: split
@@ -274,7 +256,6 @@ exit:
ret void
}
-
; 5. MemRef doesn't dominate InnerLoop's HeaderBB.
; for (int i = 0; i < n; i++) {
; r = 0;
@@ -285,16 +266,10 @@ exit:
; CHECK: --- !Missed
; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedInnerReduction
+; CHECK-NEXT: Name: Dependence
; CHECK-NEXT: Function: reduction_05
; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only supported when memory reference dominate the inner loop.
-; CHECK: --- !Missed
-; CHECK-NEXT: Pass: loop-interchange
-; CHECK-NEXT: Name: UnsupportedPHIInner
-; CHECK-NEXT: Function: reduction_05
-; CHECK-NEXT: Args:
-; CHECK-NEXT: - String: Only inner loops with induction or reduction PHI nodes can be interchange currently.
+; CHECK-NEXT: - String: Cannot interchange loops due to dependences.
; IR-LABEL: @reduction_05(
; IR-NOT: split
diff --git a/llvm/test/Transforms/LoopInterchange/reduction2mem.ll b/llvm/test/Transforms/LoopInterchange/reduction2mem.ll
index 1c19781d19eac..2486cf1e45a05 100644
--- a/llvm/test/Transforms/LoopInterchange/reduction2mem.ll
+++ b/llvm/test/Transforms/LoopInterchange/reduction2mem.ll
@@ -15,45 +15,33 @@ define void @func(ptr noalias readonly %a, ptr noalias readonly %b, ptr noalias
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[N]], 0
; CHECK-NEXT: br i1 [[CMP]], label %[[INNERLOOP_PREHEADER:.*]], label %[[EXIT:.*]]
-; CHECK: [[OUTERLOOPHEADER_PREHEADER:.*]]:
+; CHECK: [[INNERLOOP_PREHEADER]]:
; CHECK-NEXT: br label %[[OUTERLOOP_HEADER:.*]]
; CHECK: [[OUTERLOOP_HEADER]]:
-; CHECK-NEXT: [[INDEX_I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[OUTERLOOP_LATCH:.*]] ], [ 0, %[[OUTERLOOPHEADER_PREHEADER]] ]
+; CHECK-NEXT: [[INDEX_I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[OUTERLOOP_LATCH:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
; CHECK-NEXT: [[ADDR_S:%.*]] = getelementptr inbounds nuw double, ptr [[S]], i64 [[INDEX_I]]
; CHECK-NEXT: [[ADDR_A:%.*]] = getelementptr inbounds nuw double, ptr [[A]], i64 [[INDEX_I]]
; CHECK-NEXT: [[ADDR_B:%.*]] = getelementptr inbounds nuw double, ptr [[B]], i64 [[INDEX_I]]
-; CHECK-NEXT: br label %[[INNERLOOP_SPLIT1:.*]]
-; CHECK: [[INNERLOOP_PREHEADER]]:
-; CHECK-NEXT: br label %[[INNERLOOP:.*]]
-; CHECK: [[INNERLOOP]]:
-; CHECK-NEXT: [[INDEX_J:%.*]] = phi i64 [ [[J_NEXT:%.*]], %[[INNERLOOP_SPLIT:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
-; CHECK-NEXT: [[DEAD_REDUCTION:%.*]] = phi double [ [[ADD_LCSSA:%.*]], %[[INNERLOOP_SPLIT]] ], [ 0.000000e+00, %[[INNERLOOP_PREHEADER]] ]
-; CHECK-NEXT: [[FIRSTITER:%.*]] = phi i1 [ false, %[[INNERLOOP_SPLIT]] ], [ true, %[[INNERLOOP_PREHEADER]] ]
-; CHECK-NEXT: br label %[[OUTERLOOPHEADER_PREHEADER]]
-; CHECK: [[INNERLOOP_SPLIT1]]:
-; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[ADDR_S]], align 8
-; CHECK-NEXT: [[NEW_VAR:%.*]] = select i1 [[FIRSTITER]], double [[TMP0]], double 0.000000e+00
+; CHECK-NEXT: br label %[[OUTERLOOPHEADER_PREHEADER:.*]]
+; CHECK: [[OUTERLOOPHEADER_PREHEADER]]:
+; CHECK-NEXT: [[INDEX_J:%.*]] = phi i64 [ 0, %[[OUTERLOOP_HEADER]] ], [ [[J_NEXT:%.*]], %[[OUTERLOOPHEADER_PREHEADER]] ]
+; CHECK-NEXT: [[NEW_VAR:%.*]] = phi double [ 0.000000e+00, %[[OUTERLOOP_HEADER]] ], [ [[ADD:%.*]], %[[OUTERLOOPHEADER_PREHEADER]] ]
; CHECK-NEXT: [[ADDR_A_J_I:%.*]] = getelementptr inbounds nuw double, ptr [[ADDR_A]], i64 [[INDEX_J]]
; CHECK-NEXT: [[A_J_I:%.*]] = load double, ptr [[ADDR_A_J_I]], align 8
; CHECK-NEXT: [[ADDR_B_J_I:%.*]] = getelementptr inbounds nuw double, ptr [[ADDR_B]], i64 [[INDEX_J]]
; CHECK-NEXT: [[B_J_I:%.*]] = load double, ptr [[ADDR_B_J_I]], align 8
; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[B_J_I]], [[A_J_I]]
-; CHECK-NEXT: [[ADD:%.*]] = fadd fast double [[MUL]], [[NEW_VAR]]
-; CHECK-NEXT: store double [[ADD]], ptr [[ADDR_S]], align 8
-; CHECK-NEXT: [[DEAD_J_NEXT:%.*]] = add nuw nsw i64 [[INDEX_J]], 1
-; CHECK-NEXT: [[DEAD_COND:%.*]] = icmp eq i64 [[DEAD_J_NEXT]], [[N]]
-; CHECK-NEXT: br label %[[OUTERLOOP_LATCH]]
-; CHECK: [[INNERLOOP_SPLIT]]:
-; CHECK-NEXT: [[ADD_LCSSA]] = phi double [ [[ADD]], %[[OUTERLOOP_LATCH]] ]
-; CHECK-NEXT: [[DEAD_LCSSA:%.*]] = phi double [ [[ADD]], %[[OUTERLOOP_LATCH]] ]
+; CHECK-NEXT: [[ADD]] = fadd fast double [[MUL]], [[NEW_VAR]]
; CHECK-NEXT: [[J_NEXT]] = add nuw nsw i64 [[INDEX_J]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[J_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP1]], label %[[EXIT_LOOPEXIT:.*]], label %[[INNERLOOP]]
+; CHECK-NEXT: br i1 [[CMP1]], label %[[OUTERLOOP_LATCH]], label %[[OUTERLOOPHEADER_PREHEADER]]
; CHECK: [[OUTERLOOP_LATCH]]:
+; CHECK-NEXT: [[LCSSA:%.*]] = phi double [ [[ADD]], %[[OUTERLOOPHEADER_PREHEADER]] ]
+; CHECK-NEXT: store double [[LCSSA]], ptr [[ADDR_S]], align 8
; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[INDEX_I]], 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
-; CHECK-NEXT: br i1 [[CMP2]], label %[[INNERLOOP_SPLIT]], label %[[OUTERLOOP_HEADER]]
-; CHECK: [[EXIT_LOOPEXIT]]:
+; CHECK-NEXT: br i1 [[CMP2]], label %[[INNERLOOP_SPLIT:.*]], label %[[OUTERLOOP_HEADER]]
+; CHECK: [[INNERLOOP_SPLIT]]:
; CHECK-NEXT: br label %[[EXIT]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
>From f0a7e712cfaf915583f5f8d769126128c0da755e Mon Sep 17 00:00:00 2001
From: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: Sun, 8 Feb 2026 22:59:34 -0500
Subject: [PATCH 5/6] Fix remaining testcase in unroll and jam
---
.../LoopUnrollAndJam/unroll-and-jam.ll | 476 +-----------------
1 file changed, 10 insertions(+), 466 deletions(-)
diff --git a/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll b/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
index a3d2fcb5ab946..64826e6ae99eb 100644
--- a/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
+++ b/llvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
@@ -179,150 +179,14 @@ for.end:
}
+
; Tests for(i) { sum = A[i]; for(j) sum += B[j]; A[i] = sum; }
; A[i] load/store dependency should not block unroll-and-jam
+; We fail to catch the opportunity in this loop after PR #178047.
+; Improvements in DA might be possible to be able to catch this again.
define void @test2(i32 %I, i32 %E, ptr noalias nocapture %A, ptr noalias nocapture readonly %B) #0 {
; CHECK-LABEL: define void @test2(
; CHECK-SAME: i32 [[I:%.*]], i32 [[E:%.*]], ptr noalias captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[E]], 0
-; CHECK-NEXT: [[CMP125:%.*]] = icmp ne i32 [[I]], 0
-; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP]], [[CMP125]]
-; CHECK-NEXT: br i1 [[OR_COND]], label %[[FOR_OUTER_PREHEADER:.*]], label %[[FOR_END10:.*]]
-; CHECK: [[FOR_OUTER_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[I]], -1
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i32 [[I]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_OUTER_EPIL_PREHEADER:.*]], label %[[FOR_OUTER_PREHEADER_NEW:.*]]
-; CHECK: [[FOR_OUTER_PREHEADER_NEW]]:
-; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]]
-; CHECK-NEXT: br label %[[FOR_OUTER:.*]]
-; CHECK: [[FOR_OUTER]]:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD9_3:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[FOR_OUTER_PREHEADER_NEW]] ]
-; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, %[[FOR_OUTER_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[FOR_LATCH]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I]]
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9:%.*]] = add nuw nsw i32 [[I]], 1
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9]]
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_1:%.*]] = add nuw nsw i32 [[I]], 2
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_1]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_2:%.*]] = add nuw nsw i32 [[I]], 3
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_2]]
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_3]] = add nuw i32 [[I]], 4
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
-; CHECK-NEXT: br label %[[FOR_INNER:.*]]
-; CHECK: [[FOR_INNER]]:
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[INC:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[TMP2]], %[[FOR_OUTER]] ], [ [[ADD:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[INC_1:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ [[TMP3]], %[[FOR_OUTER]] ], [ [[ADD_1:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[INC_2:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ [[TMP4]], %[[FOR_OUTER]] ], [ [[ADD_2:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_3:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[INC_3:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_3:%.*]] = phi i32 [ [[TMP5]], %[[FOR_OUTER]] ], [ [[ADD_3:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J]]
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD]] = add i32 [[TMP6]], [[SUM]]
-; CHECK-NEXT: [[INC]] = add nuw i32 [[J]], 1
-; CHECK-NEXT: [[ARRAYIDX6_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_1]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX6_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_1]] = add i32 [[TMP7]], [[SUM_1]]
-; CHECK-NEXT: [[INC_1]] = add nuw i32 [[J_1]], 1
-; CHECK-NEXT: [[ARRAYIDX6_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_2]]
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX6_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_2]] = add i32 [[TMP8]], [[SUM_2]]
-; CHECK-NEXT: [[INC_2]] = add nuw i32 [[J_2]], 1
-; CHECK-NEXT: [[ARRAYIDX6_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_3]]
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX6_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_3]] = add i32 [[TMP9]], [[SUM_3]]
-; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_3]], 1
-; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[INC_3]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[FOR_LATCH]], label %[[FOR_INNER]]
-; CHECK: [[FOR_LATCH]]:
-; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD_LCSSA_1:%.*]] = phi i32 [ [[ADD_1]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD_LCSSA_2:%.*]] = phi i32 [ [[ADD_2]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD_LCSSA_3:%.*]] = phi i32 [ [[ADD_3]], %[[FOR_INNER]] ]
-; CHECK-NEXT: store i32 [[ADD_LCSSA]], ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD_LCSSA_1]], ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD_LCSSA_2]], ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD_LCSSA_3]], ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label %[[FOR_END10_LOOPEXIT_UNR_LCSSA:.*]], label %[[FOR_OUTER]], !llvm.loop [[LOOP6:![0-9]+]]
-; CHECK: [[FOR_END10_LOOPEXIT_UNR_LCSSA]]:
-; CHECK-NEXT: [[I_UNR1:%.*]] = phi i32 [ [[ADD9_3]], %[[FOR_LATCH]] ]
-; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_OUTER_EPIL_PREHEADER]], label %[[FOR_END10_LOOPEXIT:.*]]
-; CHECK: [[FOR_OUTER_EPIL_PREHEADER]]:
-; CHECK-NEXT: [[I_UNR:%.*]] = phi i32 [ 0, %[[FOR_OUTER_PREHEADER]] ], [ [[I_UNR1]], %[[FOR_END10_LOOPEXIT_UNR_LCSSA]] ]
-; CHECK-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
-; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
-; CHECK-NEXT: br label %[[FOR_OUTER_EPIL:.*]]
-; CHECK: [[FOR_OUTER_EPIL]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_UNR]]
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL:.*]]
-; CHECK: [[FOR_INNER_EPIL]]:
-; CHECK-NEXT: [[J_EPIL:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL]] ], [ [[INC_EPIL:%.*]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: [[SUM_EPIL:%.*]] = phi i32 [ [[TMP10]], %[[FOR_OUTER_EPIL]] ], [ [[ADD_EPIL:%.*]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: [[ARRAYIDX6_EPIL:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL]]
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX6_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL]] = add i32 [[TMP11]], [[SUM_EPIL]]
-; CHECK-NEXT: [[INC_EPIL]] = add nuw i32 [[J_EPIL]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL:%.*]] = icmp eq i32 [[INC_EPIL]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL]], label %[[FOR_LATCH_EPIL:.*]], label %[[FOR_INNER_EPIL]]
-; CHECK: [[FOR_LATCH_EPIL]]:
-; CHECK-NEXT: [[ADD_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD_EPIL]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL:%.*]] = add nuw i32 [[I_UNR]], 1
-; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]]
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_OUTER_EPIL_1:.*]], label %[[FOR_END10_LOOPEXIT_EPILOG_LCSSA:.*]]
-; CHECK: [[FOR_OUTER_EPIL_1]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_EPIL]]
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL_1:.*]]
-; CHECK: [[FOR_INNER_EPIL_1]]:
-; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_1]] ], [ [[INC_EPIL_1:%.*]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ [[TMP12]], %[[FOR_OUTER_EPIL_1]] ], [ [[ADD_EPIL_1:%.*]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]]
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL_1]] = add i32 [[TMP13]], [[SUM_EPIL_1]]
-; CHECK-NEXT: [[INC_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[INC_EPIL_1]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label %[[FOR_LATCH_EPIL_1:.*]], label %[[FOR_INNER_EPIL_1]]
-; CHECK: [[FOR_LATCH_EPIL_1]]:
-; CHECK-NEXT: [[ADD_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD_EPIL_1]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
-; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label %[[FOR_OUTER_EPIL_2:.*]], label %[[FOR_END10_LOOPEXIT_EPILOG_LCSSA]]
-; CHECK: [[FOR_OUTER_EPIL_2]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD9_EPIL_1]]
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL_2:.*]]
-; CHECK: [[FOR_INNER_EPIL_2]]:
-; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_2]] ], [ [[INC_EPIL_2:%.*]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ [[TMP14]], %[[FOR_OUTER_EPIL_2]] ], [ [[ADD_EPIL_2:%.*]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: [[ARRAYIDX6_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]]
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX6_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL_2]] = add i32 [[TMP15]], [[SUM_EPIL_2]]
-; CHECK-NEXT: [[INC_EPIL_2]] = add nuw i32 [[J_EPIL_2]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL_2:%.*]] = icmp eq i32 [[INC_EPIL_2]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL_2]], label %[[FOR_LATCH_EPIL_2:.*]], label %[[FOR_INNER_EPIL_2]]
-; CHECK: [[FOR_LATCH_EPIL_2]]:
-; CHECK-NEXT: [[ADD_LCSSA_EPIL_2:%.*]] = phi i32 [ [[ADD_EPIL_2]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: store i32 [[ADD_LCSSA_EPIL_2]], ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_END10_LOOPEXIT_EPILOG_LCSSA]]
-; CHECK: [[FOR_END10_LOOPEXIT_EPILOG_LCSSA]]:
-; CHECK-NEXT: br label %[[FOR_END10_LOOPEXIT]]
-; CHECK: [[FOR_END10_LOOPEXIT]]:
-; CHECK-NEXT: br label %[[FOR_END10]]
-; CHECK: [[FOR_END10]]:
-; CHECK-NEXT: ret void
-;
entry:
%cmp = icmp ne i32 %E, 0
%cmp125 = icmp ne i32 %I, 0
@@ -457,6 +321,7 @@ for.end:
}
+
; Tests Complete unroll-and-jam with a trip count of 1
define void @test4(i32 %I, i32 %E, ptr noalias nocapture %A, ptr noalias nocapture readonly %B) #0 {
; CHECK-LABEL: define void @test4(
@@ -608,7 +473,6 @@ for.end:
ret i32 0
}
-
; Test odd uses of phi nodes
@f = hidden global i32 0, align 4
define i32 @test6() #0 {
@@ -691,165 +555,14 @@ for.end:
}
+
; Has a positive dependency between two stores. Still valid.
; The negative dependecy is in unroll-and-jam-disabled.ll
+; We fail to catch the opportunity in this loop after PR #178047.
+; Improvements in DA might be possible to be able to catch this again.
define void @test7(i32 %I, i32 %E, ptr noalias nocapture %A, ptr noalias nocapture readonly %B) #0 {
; CHECK-LABEL: define void @test7(
; CHECK-SAME: i32 [[I:%.*]], i32 [[E:%.*]], ptr noalias captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[E]], 0
-; CHECK-NEXT: [[CMP128:%.*]] = icmp ne i32 [[I]], 0
-; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP128]], [[CMP]]
-; CHECK-NEXT: br i1 [[OR_COND]], label %[[FOR_PREHEADER:.*]], label %[[FOR_END:.*]]
-; CHECK: [[FOR_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[I]], -1
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i32 [[I]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_OUTER_EPIL_PREHEADER:.*]], label %[[FOR_PREHEADER_NEW:.*]]
-; CHECK: [[FOR_PREHEADER_NEW]]:
-; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]]
-; CHECK-NEXT: br label %[[FOR_OUTER:.*]]
-; CHECK: [[FOR_OUTER]]:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD_3:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[FOR_PREHEADER_NEW]] ]
-; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, %[[FOR_PREHEADER_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[FOR_LATCH]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I]], 1
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I]], 2
-; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[I]], 3
-; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_3]] = add nuw i32 [[I]], 4
-; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_3]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
-; CHECK-NEXT: br label %[[FOR_INNER:.*]]
-; CHECK: [[FOR_LATCH]]:
-; CHECK-NEXT: [[ADD9_LCSSA:%.*]] = phi i32 [ [[ADD9:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD9_LCSSA_1:%.*]] = phi i32 [ [[ADD9_1:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD9_LCSSA_2:%.*]] = phi i32 [ [[ADD9_2:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD9_LCSSA_3:%.*]] = phi i32 [ [[ADD9_3:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA]], ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_1]], ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_2]], ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_3]], ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label %[[FOR_END_LOOPEXIT_UNR_LCSSA:.*]], label %[[FOR_OUTER]], !llvm.loop [[LOOP8:![0-9]+]]
-; CHECK: [[FOR_INNER]]:
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9_1]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10_1:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9_2]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10_2:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_3:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9_3]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_3:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10_3:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J]]
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9]] = add i32 [[L1]], [[SUM]]
-; CHECK-NEXT: [[ADD10]] = add nuw i32 [[J]], 1
-; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_1]]
-; CHECK-NEXT: [[L1_1:%.*]] = load i32, ptr [[ARRAYIDX7_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_1]] = add i32 [[L1_1]], [[SUM_1]]
-; CHECK-NEXT: [[ADD10_1]] = add nuw i32 [[J_1]], 1
-; CHECK-NEXT: [[ARRAYIDX7_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_2]]
-; CHECK-NEXT: [[L1_2:%.*]] = load i32, ptr [[ARRAYIDX7_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_2]] = add i32 [[L1_2]], [[SUM_2]]
-; CHECK-NEXT: [[ADD10_2]] = add nuw i32 [[J_2]], 1
-; CHECK-NEXT: [[ARRAYIDX7_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_3]]
-; CHECK-NEXT: [[L1_3:%.*]] = load i32, ptr [[ARRAYIDX7_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_3]] = add i32 [[L1_3]], [[SUM_3]]
-; CHECK-NEXT: [[ADD10_3]] = add nuw i32 [[J_3]], 1
-; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[ADD10_3]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[FOR_LATCH]], label %[[FOR_INNER]]
-; CHECK: [[FOR_END_LOOPEXIT_UNR_LCSSA]]:
-; CHECK-NEXT: [[I_UNR1:%.*]] = phi i32 [ [[ADD_3]], %[[FOR_LATCH]] ]
-; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_OUTER_EPIL_PREHEADER]], label %[[FOR_END_LOOPEXIT:.*]]
-; CHECK: [[FOR_OUTER_EPIL_PREHEADER]]:
-; CHECK-NEXT: [[I_UNR:%.*]] = phi i32 [ 0, %[[FOR_PREHEADER]] ], [ [[I_UNR1]], %[[FOR_END_LOOPEXIT_UNR_LCSSA]] ]
-; CHECK-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
-; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
-; CHECK-NEXT: br label %[[FOR_OUTER_EPIL:.*]]
-; CHECK: [[FOR_OUTER_EPIL]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_UNR]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL:%.*]] = add nuw i32 [[I_UNR]], 1
-; CHECK-NEXT: [[ARRAYIDX2_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL:.*]]
-; CHECK: [[FOR_INNER_EPIL]]:
-; CHECK-NEXT: [[SUM_EPIL:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL]] ], [ [[ADD9_EPIL:%.*]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: [[J_EPIL:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL]] ], [ [[ADD10_EPIL:%.*]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: [[ARRAYIDX7_EPIL:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL]]
-; CHECK-NEXT: [[L1_EPIL:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL]] = add i32 [[L1_EPIL]], [[SUM_EPIL]]
-; CHECK-NEXT: [[ADD10_EPIL]] = add nuw i32 [[J_EPIL]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL:%.*]] = icmp eq i32 [[ADD10_EPIL]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL]], label %[[FOR_LATCH_EPIL:.*]], label %[[FOR_INNER_EPIL]]
-; CHECK: [[FOR_LATCH_EPIL]]:
-; CHECK-NEXT: [[ADD9_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD9_EPIL]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]]
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_OUTER_EPIL_1:.*]], label %[[FOR_END_LOOPEXIT_EPILOG_LCSSA:.*]]
-; CHECK: [[FOR_OUTER_EPIL_1]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
-; CHECK-NEXT: [[ARRAYIDX2_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL_1:.*]]
-; CHECK: [[FOR_INNER_EPIL_1]]:
-; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_1]] ], [ [[ADD9_EPIL_1:%.*]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_1]] ], [ [[ADD10_EPIL_1:%.*]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: [[ARRAYIDX7_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]]
-; CHECK-NEXT: [[L1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL_1]] = add i32 [[L1_EPIL_1]], [[SUM_EPIL_1]]
-; CHECK-NEXT: [[ADD10_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[ADD10_EPIL_1]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label %[[FOR_LATCH_EPIL_1:.*]], label %[[FOR_INNER_EPIL_1]]
-; CHECK: [[FOR_LATCH_EPIL_1]]:
-; CHECK-NEXT: [[ADD9_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD9_EPIL_1]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label %[[FOR_OUTER_EPIL_2:.*]], label %[[FOR_END_LOOPEXIT_EPILOG_LCSSA]]
-; CHECK: [[FOR_OUTER_EPIL_2]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add nuw i32 [[I_UNR]], 3
-; CHECK-NEXT: [[ARRAYIDX2_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_2]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX2_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL_2:.*]]
-; CHECK: [[FOR_INNER_EPIL_2]]:
-; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_2]] ], [ [[ADD9_EPIL_2:%.*]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_2]] ], [ [[ADD10_EPIL_2:%.*]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: [[ARRAYIDX7_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]]
-; CHECK-NEXT: [[L1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX7_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL_2]] = add i32 [[L1_EPIL_2]], [[SUM_EPIL_2]]
-; CHECK-NEXT: [[ADD10_EPIL_2]] = add nuw i32 [[J_EPIL_2]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL_2:%.*]] = icmp eq i32 [[ADD10_EPIL_2]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL_2]], label %[[FOR_LATCH_EPIL_2:.*]], label %[[FOR_INNER_EPIL_2]]
-; CHECK: [[FOR_LATCH_EPIL_2]]:
-; CHECK-NEXT: [[ADD9_LCSSA_EPIL_2:%.*]] = phi i32 [ [[ADD9_EPIL_2]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_2]], ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_END_LOOPEXIT_EPILOG_LCSSA]]
-; CHECK: [[FOR_END_LOOPEXIT_EPILOG_LCSSA]]:
-; CHECK-NEXT: br label %[[FOR_END_LOOPEXIT]]
-; CHECK: [[FOR_END_LOOPEXIT]]:
-; CHECK-NEXT: br label %[[FOR_END]]
-; CHECK: [[FOR_END]]:
-; CHECK-NEXT: ret void
-;
entry:
%cmp = icmp ne i32 %E, 0
%cmp128 = icmp ne i32 %I, 0
@@ -888,171 +601,13 @@ for.end:
}
+
; Same as test7 with an extra outer loop nest
+; We fail to catch the opportunity in this loop after PR #178047.
+; Improvements in DA might be possible to be able to catch this again.
define void @test8(i32 %I, i32 %E, ptr noalias nocapture %A, ptr noalias nocapture readonly %B) #0 {
; CHECK-LABEL: define void @test8(
; CHECK-SAME: i32 [[I:%.*]], i32 [[E:%.*]], ptr noalias captures(none) [[A:%.*]], ptr noalias readonly captures(none) [[B:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[E]], 0
-; CHECK-NEXT: [[CMP336:%.*]] = icmp eq i32 [[I]], 0
-; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP336]]
-; CHECK-NEXT: br i1 [[OR_COND]], label %[[FOR_END:.*]], label %[[FOR_PREHEADER:.*]]
-; CHECK: [[FOR_PREHEADER]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[I]], -1
-; CHECK-NEXT: br label %[[FOR_OUTEST:.*]]
-; CHECK: [[FOR_OUTEST]]:
-; CHECK-NEXT: [[X_038:%.*]] = phi i32 [ [[INC:%.*]], %[[FOR_CLEANUP:.*]] ], [ 0, %[[FOR_PREHEADER]] ]
-; CHECK-NEXT: [[XTRAITER:%.*]] = and i32 [[I]], 3
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 3
-; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_OUTER_EPIL_PREHEADER:.*]], label %[[FOR_OUTEST_NEW:.*]]
-; CHECK: [[FOR_OUTEST_NEW]]:
-; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i32 [[I]], [[XTRAITER]]
-; CHECK-NEXT: br label %[[FOR_OUTER:.*]]
-; CHECK: [[FOR_OUTER]]:
-; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[ADD_3:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[FOR_OUTEST_NEW]] ]
-; CHECK-NEXT: [[NITER:%.*]] = phi i32 [ 0, %[[FOR_OUTEST_NEW]] ], [ [[NITER_NEXT_3:%.*]], %[[FOR_LATCH]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[I]], 1
-; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[I]], 2
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_1]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_4]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[I]], 3
-; CHECK-NEXT: [[ARRAYIDX6_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_2]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_3]] = add nuw i32 [[I]], 4
-; CHECK-NEXT: [[ARRAYIDX6_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_3]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[NITER_NEXT_3]] = add i32 [[NITER]], 4
-; CHECK-NEXT: br label %[[FOR_INNER:.*]]
-; CHECK: [[FOR_INNER]]:
-; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9_1:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10_1:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9_2:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10_2:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[SUM_3:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD9_3:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[J_3:%.*]] = phi i32 [ 0, %[[FOR_OUTER]] ], [ [[ADD10_3:%.*]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J]]
-; CHECK-NEXT: [[L1:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9]] = add i32 [[L1]], [[SUM]]
-; CHECK-NEXT: [[ADD10]] = add nuw i32 [[J]], 1
-; CHECK-NEXT: [[ARRAYIDX11_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_1]]
-; CHECK-NEXT: [[L1_1:%.*]] = load i32, ptr [[ARRAYIDX11_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_1]] = add i32 [[L1_1]], [[SUM_1]]
-; CHECK-NEXT: [[ADD10_1]] = add nuw i32 [[J_1]], 1
-; CHECK-NEXT: [[ARRAYIDX11_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_2]]
-; CHECK-NEXT: [[L1_2:%.*]] = load i32, ptr [[ARRAYIDX11_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_2]] = add i32 [[L1_2]], [[SUM_2]]
-; CHECK-NEXT: [[ADD10_2]] = add nuw i32 [[J_2]], 1
-; CHECK-NEXT: [[ARRAYIDX11_3:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_3]]
-; CHECK-NEXT: [[L1_3:%.*]] = load i32, ptr [[ARRAYIDX11_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_3]] = add i32 [[L1_3]], [[SUM_3]]
-; CHECK-NEXT: [[ADD10_3]] = add nuw i32 [[J_3]], 1
-; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[ADD10_3]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_3]], label %[[FOR_LATCH]], label %[[FOR_INNER]]
-; CHECK: [[FOR_LATCH]]:
-; CHECK-NEXT: [[ADD9_LCSSA:%.*]] = phi i32 [ [[ADD9]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD9_LCSSA_1:%.*]] = phi i32 [ [[ADD9_1]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD9_LCSSA_2:%.*]] = phi i32 [ [[ADD9_2]], %[[FOR_INNER]] ]
-; CHECK-NEXT: [[ADD9_LCSSA_3:%.*]] = phi i32 [ [[ADD9_3]], %[[FOR_INNER]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA]], ptr [[ARRAYIDX]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_1]], ptr [[ARRAYIDX_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_2]], ptr [[ARRAYIDX_4]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_3]], ptr [[ARRAYIDX_3]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i32 [[NITER_NEXT_3]], [[UNROLL_ITER]]
-; CHECK-NEXT: br i1 [[NITER_NCMP_3]], label %[[FOR_CLEANUP_UNR_LCSSA:.*]], label %[[FOR_OUTER]], !llvm.loop [[LOOP9:![0-9]+]]
-; CHECK: [[FOR_CLEANUP_UNR_LCSSA]]:
-; CHECK-NEXT: [[I_UNR1:%.*]] = phi i32 [ [[ADD_3]], %[[FOR_LATCH]] ]
-; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i32 [[XTRAITER]], 0
-; CHECK-NEXT: br i1 [[LCMP_MOD]], label %[[FOR_OUTER_EPIL_PREHEADER]], label %[[FOR_CLEANUP]]
-; CHECK: [[FOR_OUTER_EPIL_PREHEADER]]:
-; CHECK-NEXT: [[I_UNR:%.*]] = phi i32 [ 0, %[[FOR_OUTEST]] ], [ [[I_UNR1]], %[[FOR_CLEANUP_UNR_LCSSA]] ]
-; CHECK-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0
-; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]])
-; CHECK-NEXT: br label %[[FOR_OUTER_EPIL:.*]]
-; CHECK: [[FOR_OUTER_EPIL]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[I_UNR]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL:%.*]] = add nuw i32 [[I_UNR]], 1
-; CHECK-NEXT: [[ARRAYIDX6_EPIL:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL:.*]]
-; CHECK: [[FOR_INNER_EPIL]]:
-; CHECK-NEXT: [[SUM_EPIL:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL]] ], [ [[ADD9_EPIL:%.*]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: [[J_EPIL:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL]] ], [ [[ADD10_EPIL:%.*]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: [[ARRAYIDX11_EPIL:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL]]
-; CHECK-NEXT: [[L1_EPIL:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL]] = add i32 [[L1_EPIL]], [[SUM_EPIL]]
-; CHECK-NEXT: [[ADD10_EPIL]] = add nuw i32 [[J_EPIL]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL:%.*]] = icmp eq i32 [[ADD10_EPIL]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL]], label %[[FOR_LATCH_EPIL:.*]], label %[[FOR_INNER_EPIL]]
-; CHECK: [[FOR_LATCH_EPIL]]:
-; CHECK-NEXT: [[ADD9_LCSSA_EPIL:%.*]] = phi i32 [ [[ADD9_EPIL]], %[[FOR_INNER_EPIL]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL]], ptr [[ARRAYIDX_EPIL]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i32 1, [[XTRAITER]]
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label %[[FOR_OUTER_EPIL_1:.*]], label %[[FOR_CLEANUP_EPILOG_LCSSA:.*]]
-; CHECK: [[FOR_OUTER_EPIL_1]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL_1:%.*]] = add nuw i32 [[I_UNR]], 2
-; CHECK-NEXT: [[ARRAYIDX6_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL_1:.*]]
-; CHECK: [[FOR_INNER_EPIL_1]]:
-; CHECK-NEXT: [[SUM_EPIL_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_1]] ], [ [[ADD9_EPIL_1:%.*]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: [[J_EPIL_1:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_1]] ], [ [[ADD10_EPIL_1:%.*]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: [[ARRAYIDX11_EPIL_1:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_1]]
-; CHECK-NEXT: [[L1_EPIL_1:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL_1]] = add i32 [[L1_EPIL_1]], [[SUM_EPIL_1]]
-; CHECK-NEXT: [[ADD10_EPIL_1]] = add nuw i32 [[J_EPIL_1]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL_1:%.*]] = icmp eq i32 [[ADD10_EPIL_1]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL_1]], label %[[FOR_LATCH_EPIL_1:.*]], label %[[FOR_INNER_EPIL_1]]
-; CHECK: [[FOR_LATCH_EPIL_1]]:
-; CHECK-NEXT: [[ADD9_LCSSA_EPIL_1:%.*]] = phi i32 [ [[ADD9_EPIL_1]], %[[FOR_INNER_EPIL_1]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_1]], ptr [[ARRAYIDX_EPIL_1]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[EPIL_ITER_CMP_1:%.*]] = icmp ne i32 2, [[XTRAITER]]
-; CHECK-NEXT: br i1 [[EPIL_ITER_CMP_1]], label %[[FOR_OUTER_EPIL_2:.*]], label %[[FOR_CLEANUP_EPILOG_LCSSA]]
-; CHECK: [[FOR_OUTER_EPIL_2]]:
-; CHECK-NEXT: [[ARRAYIDX_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_1]]
-; CHECK-NEXT: store i32 0, ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD_EPIL_2:%.*]] = add nuw i32 [[I_UNR]], 3
-; CHECK-NEXT: [[ARRAYIDX6_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i32 [[ADD_EPIL_2]]
-; CHECK-NEXT: store i32 2, ptr [[ARRAYIDX6_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_INNER_EPIL_2:.*]]
-; CHECK: [[FOR_INNER_EPIL_2]]:
-; CHECK-NEXT: [[SUM_EPIL_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_2]] ], [ [[ADD9_EPIL_2:%.*]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: [[J_EPIL_2:%.*]] = phi i32 [ 0, %[[FOR_OUTER_EPIL_2]] ], [ [[ADD10_EPIL_2:%.*]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: [[ARRAYIDX11_EPIL_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i32 [[J_EPIL_2]]
-; CHECK-NEXT: [[L1_EPIL_2:%.*]] = load i32, ptr [[ARRAYIDX11_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: [[ADD9_EPIL_2]] = add i32 [[L1_EPIL_2]], [[SUM_EPIL_2]]
-; CHECK-NEXT: [[ADD10_EPIL_2]] = add nuw i32 [[J_EPIL_2]], 1
-; CHECK-NEXT: [[EXITCOND_EPIL_2:%.*]] = icmp eq i32 [[ADD10_EPIL_2]], [[E]]
-; CHECK-NEXT: br i1 [[EXITCOND_EPIL_2]], label %[[FOR_LATCH_EPIL_2:.*]], label %[[FOR_INNER_EPIL_2]]
-; CHECK: [[FOR_LATCH_EPIL_2]]:
-; CHECK-NEXT: [[ADD9_LCSSA_EPIL_2:%.*]] = phi i32 [ [[ADD9_EPIL_2]], %[[FOR_INNER_EPIL_2]] ]
-; CHECK-NEXT: store i32 [[ADD9_LCSSA_EPIL_2]], ptr [[ARRAYIDX_EPIL_2]], align 4, !tbaa [[INT_TBAA0]]
-; CHECK-NEXT: br label %[[FOR_CLEANUP_EPILOG_LCSSA]]
-; CHECK: [[FOR_CLEANUP_EPILOG_LCSSA]]:
-; CHECK-NEXT: br label %[[FOR_CLEANUP]]
-; CHECK: [[FOR_CLEANUP]]:
-; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[X_038]], 1
-; CHECK-NEXT: [[EXITCOND41:%.*]] = icmp eq i32 [[INC]], 5
-; CHECK-NEXT: br i1 [[EXITCOND41]], label %[[FOR_END_LOOPEXIT:.*]], label %[[FOR_OUTEST]]
-; CHECK: [[FOR_END_LOOPEXIT]]:
-; CHECK-NEXT: br label %[[FOR_END]]
-; CHECK: [[FOR_END]]:
-; CHECK-NEXT: ret void
-;
entry:
%cmp = icmp eq i32 %E, 0
%cmp336 = icmp eq i32 %I, 0
@@ -1099,7 +654,6 @@ for.end:
ret void
}
-
; Same as test1 with tbaa, not noalias
define void @test9(i32 %I, i32 %E, ptr nocapture %A, ptr nocapture readonly %B) #0 {
; CHECK-LABEL: define void @test9(
@@ -1282,7 +836,6 @@ for.end:
ret void
}
-
; Be careful not to incorrectly update the exit phi nodes
%struct.a = type { i64 }
@g = common global %struct.a zeroinitializer, align 8
@@ -1445,7 +998,6 @@ for.end26:
ret i16 0
}
-
!5 = !{!6, !6, i64 0}
!6 = !{!"int", !7, i64 0}
!7 = !{!"omnipotent char", !8, i64 0}
@@ -1459,12 +1011,4 @@ for.end26:
; CHECK: [[META3]] = !{!"Simple C/C++ TBAA"}
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]}
; CHECK: [[META5]] = !{!"llvm.loop.unroll.disable"}
-; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]}
-; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]}
-; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]}
-; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]]}
-; CHECK: [[SHORT_TBAA10]] = !{[[META11:![0-9]+]], [[META11]], i64 0}
-; CHECK: [[META11]] = !{!"short", [[META2]], i64 0}
-; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]}
-; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]}
;.
>From 49baeb7eb8692566b0b81c88a6c565ae031c8214 Mon Sep 17 00:00:00 2001
From: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: Mon, 9 Feb 2026 06:36:55 -0500
Subject: [PATCH 6/6] remove BTC sign check
---
llvm/lib/Analysis/DependenceAnalysis.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Analysis/DependenceAnalysis.cpp b/llvm/lib/Analysis/DependenceAnalysis.cpp
index 204aa65a8fbc9..bec04f95a12f4 100644
--- a/llvm/lib/Analysis/DependenceAnalysis.cpp
+++ b/llvm/lib/Analysis/DependenceAnalysis.cpp
@@ -1364,7 +1364,7 @@ bool DependenceInfo::strongSIVtest(const SCEV *Coeff, const SCEV *SrcConst,
// check that |Delta| < iteration count
bool IsDeltaLarge = [&] {
const SCEV *UpperBound = collectUpperBound(CurSrcLoop, Delta->getType());
- if (!UpperBound || !SE->isKnownNonNegative(UpperBound))
+ if (!UpperBound)
return false;
LLVM_DEBUG(dbgs() << "\t UpperBound = " << *UpperBound);
LLVM_DEBUG(dbgs() << ", " << *UpperBound->getType() << "\n");
@@ -2416,8 +2416,8 @@ bool DependenceInfo::testSIV(const SCEV *Src, const SCEV *Dst, unsigned &Level,
LLVM_DEBUG(dbgs() << " dst = " << *Dst << "\n");
const SCEVAddRecExpr *SrcAddRec = dyn_cast<SCEVAddRecExpr>(Src);
const SCEVAddRecExpr *DstAddRec = dyn_cast<SCEVAddRecExpr>(Dst);
- bool SrcAnalyzable = SrcAddRec && SrcAddRec->hasNoSignedWrap();
- bool DstAnalyzable = DstAddRec && DstAddRec->hasNoSignedWrap();
+ bool SrcAnalyzable = SrcAddRec != nullptr && SrcAddRec->hasNoSignedWrap();
+ bool DstAnalyzable = DstAddRec != nullptr && DstAddRec->hasNoSignedWrap();
if (SrcAnalyzable && DstAnalyzable) {
const SCEV *SrcConst = SrcAddRec->getStart();
const SCEV *DstConst = DstAddRec->getStart();
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