[llvm] [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (PR #180472)

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woruyu wrote:

I have a few questions about the correct/expected SelectionDAG form here:

1) When building a BUILD_VECTOR, I used MVT::i8 constants as operands, but the result type is vXi1. Is it valid/expected for BUILD_VECTOR operands to be wider than the vector element type (i8 operands for a vXi1 result), or should the operands always match the element type (i1) exactly?

2) If I build the vector with i1 constants (the “obvious” form for vXi1), I hit an assertion during DAG legalization because i1 is illegal on X86 and gets promoted (TypePromoteInteger). Is there a recommended way to materialize a vXi1 mask constant without tripping LegalizeDAG’s illegal-type checks?

3) In my current approach, the vXi1 BUILD_VECTOR ends up being rewritten in LowerBUILD_VECTOR into a bitcast plus EXTRACT_SUBVECTOR (e.g. i8 -> v8i1 -> extract_subvector -> v4i1). Is it acceptable to rely on this lowering/rewriting to obtain a legal form, or should the original lowering avoid creating vXi1 (or i1) nodes and instead directly construct the final legal representation?

Any guidance on the intended canonical DAG shape for vXi1 mask constants on X86 would be appreciated.

https://github.com/llvm/llvm-project/pull/180472