[llvm] [X86] Fix lower1BitShuffle blend-with-zero shuffles to AND mask (PR #180472)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: woruyu (woruyu)

<details>
<summary>Changes</summary>

### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/180426.

---
Full diff: https://github.com/llvm/llvm-project/pull/180472.diff


2 Files Affected:

- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+9-3) 
- (modified) llvm/test/CodeGen/X86/avx512bwvl-arith.ll (+15) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8d9359b6fc3d2..ac7db1eaea597 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18361,9 +18361,15 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
     return Zeroable[M.index()] || (M.value() == (int)M.index());
   });
   if (IsBlendWithZero) {
-    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
-    SDValue BlendMask = DAG.getConstant(~Zeroable, DL, IntVT);
-    return DAG.getNode(ISD::AND, DL, VT, V1, DAG.getBitcast(VT, BlendMask));
+    SmallVector<SDValue, 32> MaskElts;
+    MaskElts.reserve(NumElts);
+
+    for (int I = 0; I != NumElts; ++I) {
+      MaskElts.push_back(DAG.getConstant(Zeroable[I] ? 0 : 1, DL, MVT::i8));
+    }
+
+    SDValue MaskVec = DAG.getBuildVector(VT, DL, MaskElts);
+    return DAG.getNode(ISD::AND, DL, VT, V1, MaskVec);
   }
 
   MVT ExtVT;
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
index decab7b485c4d..f62f02d44bfeb 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
@@ -250,3 +250,18 @@ define i16 @PR90356(<16 x i1> %a) {
   %2 = bitcast <16 x i1> %1 to i16
   ret i16 %2
 }
+
+define <4 x i1> @ISSUE180426(<4 x i1> %0) {
+; CHECK-LABEL: ISSUE180426:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT:    movb $5, %al
+; CHECK-NEXT:    kmovd %eax, %k1
+; CHECK-NEXT:    vptestmd %xmm0, %xmm0, %k1 {%k1}
+; CHECK-NEXT:    vpcmpeqd %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovdqa32 %xmm0, %xmm0 {%k1} {z}
+; CHECK-NEXT:    retq
+entry:
+  %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  ret <4 x i1> %1
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/180472