[llvm] [RISCV] Relax codegen predicates for HINT-based instructions (PR #179872)

[Kito Cheng via llvm-commits]

kito-cheng wrote:

This change remind me prefetch is also a HINT as well (reuse ORI instruction), however it's different than other HINT instruction which come from `zihint*` extension, but I think that would be better address later instead mix more thing here.

Ref:
https://docs.riscv.org/reference/isa/unpriv/cmo.html
https://docs.riscv.org/reference/isa/unpriv/cmo.html#Zicbop
```
A cache-block prefetch instruction is a HINT to the hardware that software expects to perform a particular type of memory access in the near future. Additional details are described in [Cache-Block Prefetch Instructions](https://docs.riscv.org/reference/isa/unpriv/cmo.html#Zicbop).
```

Changes:
- Add more test on `riscv-zihintpause.ll`
- Merge check lines on `prefetch.ll` because `ntl.*` can be emit unconditionally now.




https://github.com/llvm/llvm-project/pull/179872