[llvm] [RISCV] Relax codegen predicates for HINT-based instructions (PR #179872)
Kito Cheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 23:34:04 PST 2026
https://github.com/kito-cheng updated https://github.com/llvm/llvm-project/pull/179872
>From 37034f9fb350e6c3a42e3d3df6f65bc1b2c479bb Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 29 Jan 2026 15:29:59 +0800
Subject: [PATCH 1/3] [RISCV] Relax codegen predicates for HINT-based
instructions
Following the assembler/disassembler changes in #178609,
this patch also relaxes the codegen predicates for HINT-based
instructions. Since these instructions use encodings that are
architecturally guaranteed not to trap, the compiler can safely
generate them regardless of extension availability.
Changes:
- int_riscv_pause: Remove HasStdExtZihintpause predicate. The pause
intrinsic now generates the FENCE hint encoding unconditionally.
- NTL hints: Remove hasStdExtZihintntl() check in emitNTLHint().
Non-temporal locality hints are now emitted for all nontemporal
memory operations.
---
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 8 +--
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 4 +-
llvm/test/CodeGen/RISCV/prefetch.ll | 84 +++++++++++++++++++++++
llvm/test/CodeGen/RISCV/xmips-cbop.ll | 8 +++
4 files changed, 98 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 9740123d3859e..67e9c9585e25c 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -273,11 +273,11 @@ bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
// instructions) auto-generated.
#include "RISCVGenMCPseudoLowering.inc"
-// If the target supports Zihintntl and the instruction has a nontemporal
-// MachineMemOperand, emit an NTLH hint instruction before it.
+// If the instruction has a nontemporal MachineMemOperand, emit an NTL hint
+// instruction before it. NTL hints are always safe to emit since they use
+// HINT encodings that are guaranteed not to trap
+// (riscv-non-isa/riscv-elf-psabi-doc#474).
void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
- if (!STI->hasStdExtZihintntl())
- return;
if (MI->memoperands_empty())
return;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 156e41ede2d1e..71b88ebbba072 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2316,8 +2316,8 @@ def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>;
// Zihintpause
//===----------------------------------------------------------------------===//
-// Zihintpause
-let Predicates = [HasStdExtZihintpause] in
+// int_riscv_pause is always available since pause is a HINT encoding that is
+// guaranteed not to trap (riscv-non-isa/riscv-elf-psabi-doc#474).
def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll
index ba33ed7ac1a59..79cb5e0c6e85f 100644
--- a/llvm/test/CodeGen/RISCV/prefetch.ll
+++ b/llvm/test/CodeGen/RISCV/prefetch.ll
@@ -21,11 +21,13 @@ define void @test_prefetch_read_locality_0(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_read_locality_0:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_read_locality_0:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -49,11 +51,13 @@ define void @test_prefetch_write_locality_0(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_write_locality_0:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.w 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_write_locality_0:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.w 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -77,11 +81,13 @@ define void @test_prefetch_instruction_locality_0(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_0:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.i 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_0:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.i 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -105,11 +111,13 @@ define void @test_prefetch_read_locality_1(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_read_locality_1:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.pall
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_read_locality_1:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.pall
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -133,11 +141,13 @@ define void @test_prefetch_write_locality_1(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_write_locality_1:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.pall
; RV32ZICBOP-NEXT: prefetch.w 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_write_locality_1:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.pall
; RV64ZICBOP-NEXT: prefetch.w 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -161,11 +171,13 @@ define void @test_prefetch_instruction_locality_1(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_1:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.pall
; RV32ZICBOP-NEXT: prefetch.i 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_1:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.pall
; RV64ZICBOP-NEXT: prefetch.i 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -189,11 +201,13 @@ define void @test_prefetch_read_locality_2(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_read_locality_2:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.p1
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_read_locality_2:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.p1
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -217,11 +231,13 @@ define void @test_prefetch_write_locality_2(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_write_locality_2:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.p1
; RV32ZICBOP-NEXT: prefetch.w 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_write_locality_2:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.p1
; RV64ZICBOP-NEXT: prefetch.w 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -245,11 +261,13 @@ define void @test_prefetch_instruction_locality_2(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_2:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.p1
; RV32ZICBOP-NEXT: prefetch.i 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_2:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.p1
; RV64ZICBOP-NEXT: prefetch.i 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -354,11 +372,13 @@ define void @test_prefetch_offsetable_0(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_offsetable_0:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_0:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -383,11 +403,13 @@ define void @test_prefetch_offsetable_1(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_offsetable_1:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_1:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -412,11 +434,13 @@ define void @test_prefetch_offsetable_2(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_offsetable_2:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 32(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_2:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 32(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -441,11 +465,13 @@ define void @test_prefetch_offsetable_3(ptr %a) nounwind {
;
; RV32ZICBOP-LABEL: test_prefetch_offsetable_3:
; RV32ZICBOP: # %bb.0:
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -32(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_3:
; RV64ZICBOP: # %bb.0:
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -32(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -471,12 +497,14 @@ define void @test_prefetch_offsetable_4(ptr %a) nounwind {
; RV32ZICBOP-LABEL: test_prefetch_offsetable_4:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi a0, a0, 32
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_4:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi a0, a0, 32
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -503,12 +531,14 @@ define void @test_prefetch_offsetable_5(ptr %a) nounwind {
; RV32ZICBOP-LABEL: test_prefetch_offsetable_5:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi a0, a0, -1
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_5:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi a0, a0, -1
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -535,12 +565,14 @@ define void @test_prefetch_offsetable_6(ptr %a) nounwind {
; RV32ZICBOP-LABEL: test_prefetch_offsetable_6:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi a0, a0, 16
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_6:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi a0, a0, 16
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -567,12 +599,14 @@ define void @test_prefetch_offsetable_7(ptr %a) nounwind {
; RV32ZICBOP-LABEL: test_prefetch_offsetable_7:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi a0, a0, -16
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_offsetable_7:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi a0, a0, -16
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -600,6 +634,7 @@ define void @test_prefetch_offsetable_9(ptr %a) nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a1, 1
; RV32ZICBOP-NEXT: add a0, a0, a1
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 64(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -607,6 +642,7 @@ define void @test_prefetch_offsetable_9(ptr %a) nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a1, 1
; RV64ZICBOP-NEXT: add a0, a0, a1
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 64(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -635,6 +671,7 @@ define void @test_prefetch_offsetable_8(ptr %a) nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a1, 1048575
; RV32ZICBOP-NEXT: add a0, a0, a1
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -64(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -642,6 +679,7 @@ define void @test_prefetch_offsetable_8(ptr %a) nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a1, 1048575
; RV64ZICBOP-NEXT: add a0, a0, a1
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -64(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -673,6 +711,7 @@ define void @test_prefetch_frameindex_0() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_frameindex_0:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(sp)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -680,6 +719,7 @@ define void @test_prefetch_frameindex_0() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_frameindex_0:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(sp)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -725,6 +765,7 @@ define void @test_prefetch_frameindex_1() nounwind {
; RV32ZICBOP-NEXT: addi a0, a0, 16
; RV32ZICBOP-NEXT: sub sp, sp, a0
; RV32ZICBOP-NEXT: addi a0, sp, 16
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: lui a0, 1
; RV32ZICBOP-NEXT: addi a0, a0, 16
@@ -737,6 +778,7 @@ define void @test_prefetch_frameindex_1() nounwind {
; RV64ZICBOP-NEXT: addi a0, a0, 16
; RV64ZICBOP-NEXT: sub sp, sp, a0
; RV64ZICBOP-NEXT: addi a0, sp, 16
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: lui a0, 1
; RV64ZICBOP-NEXT: addi a0, a0, 16
@@ -778,6 +820,7 @@ define void @test_prefetch_frameindex_2() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
; RV32ZICBOP-NEXT: addi a0, sp, 16
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -786,6 +829,7 @@ define void @test_prefetch_frameindex_2() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
; RV64ZICBOP-NEXT: addi a0, sp, 16
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -822,6 +866,7 @@ define void @test_prefetch_frameindex_3() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
; RV32ZICBOP-NEXT: addi a0, sp, -16
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -830,6 +875,7 @@ define void @test_prefetch_frameindex_3() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
; RV64ZICBOP-NEXT: addi a0, sp, -16
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -865,6 +911,7 @@ define void @test_prefetch_frameindex_4() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_frameindex_4:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 32(sp)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -872,6 +919,7 @@ define void @test_prefetch_frameindex_4() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_frameindex_4:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 32(sp)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -906,6 +954,7 @@ define void @test_prefetch_frameindex_5() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_frameindex_5:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -32(sp)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -913,6 +962,7 @@ define void @test_prefetch_frameindex_5() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_frameindex_5:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -32(sp)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -947,6 +997,7 @@ define void @test_prefetch_frameindex_6() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_frameindex_6:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 2016(sp)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -954,6 +1005,7 @@ define void @test_prefetch_frameindex_6() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_frameindex_6:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 2016(sp)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -988,6 +1040,7 @@ define void @test_prefetch_frameindex_7() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_frameindex_7:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -2048(sp)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -995,6 +1048,7 @@ define void @test_prefetch_frameindex_7() nounwind {
; RV64ZICBOP-LABEL: test_prefetch_frameindex_7:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -2048(sp)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -1030,6 +1084,7 @@ define void @test_prefetch_frameindex_8() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: addi sp, sp, -512
; RV32ZICBOP-NEXT: addi a0, sp, 2020
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -1038,6 +1093,7 @@ define void @test_prefetch_frameindex_8() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: addi sp, sp, -512
; RV64ZICBOP-NEXT: addi a0, sp, 2020
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -1075,6 +1131,7 @@ define void @test_prefetch_frameindex_9() nounwind {
; RV32ZICBOP-NEXT: addi sp, sp, -512
; RV32ZICBOP-NEXT: mv a0, sp
; RV32ZICBOP-NEXT: addi a0, a0, -4
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
; RV32ZICBOP-NEXT: addi sp, sp, 512
; RV32ZICBOP-NEXT: ret
@@ -1084,6 +1141,7 @@ define void @test_prefetch_frameindex_9() nounwind {
; RV64ZICBOP-NEXT: addi sp, sp, -512
; RV64ZICBOP-NEXT: mv a0, sp
; RV64ZICBOP-NEXT: addi a0, a0, -4
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
; RV64ZICBOP-NEXT: addi sp, sp, 512
; RV64ZICBOP-NEXT: ret
@@ -1116,12 +1174,14 @@ define void @test_prefetch_constant_address_0() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_constant_address_0:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, 1
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 32(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_constant_address_0:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 32(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1149,6 +1209,7 @@ define void @test_prefetch_constant_address_1() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, 1
; RV32ZICBOP-NEXT: addi a0, a0, 31
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1156,6 +1217,7 @@ define void @test_prefetch_constant_address_1() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1
; RV64ZICBOP-NEXT: addi a0, a0, 31
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1183,12 +1245,14 @@ define void @test_prefetch_constant_address_2() nounwind {
; RV32ZICBOP-LABEL: test_prefetch_constant_address_2:
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, 1048561
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 32(a0)
; RV32ZICBOP-NEXT: ret
;
; RV64ZICBOP-LABEL: test_prefetch_constant_address_2:
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1048561
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 32(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1216,6 +1280,7 @@ define void @test_prefetch_constant_address_3() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, 1048561
; RV32ZICBOP-NEXT: addi a0, a0, 31
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1223,6 +1288,7 @@ define void @test_prefetch_constant_address_3() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, 1048561
; RV64ZICBOP-NEXT: addi a0, a0, 31
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1253,6 +1319,7 @@ define void @test_prefetch_global_0() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1260,6 +1327,7 @@ define void @test_prefetch_global_0() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1288,6 +1356,7 @@ define void @test_prefetch_global_1() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g+16)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+16)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1295,6 +1364,7 @@ define void @test_prefetch_global_1() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g+16)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+16)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1323,6 +1393,7 @@ define void @test_prefetch_global_2() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g-16)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-16)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1330,6 +1401,7 @@ define void @test_prefetch_global_2() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g-16)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-16)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1358,6 +1430,7 @@ define void @test_prefetch_global_3() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 32(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1365,6 +1438,7 @@ define void @test_prefetch_global_3() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 32(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1393,6 +1467,7 @@ define void @test_prefetch_global_4() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -32(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1400,6 +1475,7 @@ define void @test_prefetch_global_4() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -32(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1428,6 +1504,7 @@ define void @test_prefetch_global_5() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1435,6 +1512,7 @@ define void @test_prefetch_global_5() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1463,6 +1541,7 @@ define void @test_prefetch_global_6() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1470,6 +1549,7 @@ define void @test_prefetch_global_6() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1498,6 +1578,7 @@ define void @test_prefetch_global_7() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g+2020)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r 0(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1505,6 +1586,7 @@ define void @test_prefetch_global_7() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g+2020)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r 0(a0)
; RV64ZICBOP-NEXT: ret
;
@@ -1533,6 +1615,7 @@ define void @test_prefetch_global_8() nounwind {
; RV32ZICBOP: # %bb.0:
; RV32ZICBOP-NEXT: lui a0, %hi(g-4)
; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-4)
+; RV32ZICBOP-NEXT: ntl.all
; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
; RV32ZICBOP-NEXT: ret
;
@@ -1540,6 +1623,7 @@ define void @test_prefetch_global_8() nounwind {
; RV64ZICBOP: # %bb.0:
; RV64ZICBOP-NEXT: lui a0, %hi(g-4)
; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-4)
+; RV64ZICBOP-NEXT: ntl.all
; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
; RV64ZICBOP-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
index 0d5defc833763..32e415471267c 100644
--- a/llvm/test/CodeGen/RISCV/xmips-cbop.ll
+++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -7,11 +7,13 @@
define void @prefetch_data_read(ptr noundef %ptr) nounwind {
; RV32XMIPSPREFETCH-LABEL: prefetch_data_read:
; RV32XMIPSPREFETCH: # %bb.0: # %entry
+; RV32XMIPSPREFETCH-NEXT: ntl.all
; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 1(a0)
; RV32XMIPSPREFETCH-NEXT: ret
;
; RV64XMIPSPREFETCH-LABEL: prefetch_data_read:
; RV64XMIPSPREFETCH: # %bb.0: # %entry
+; RV64XMIPSPREFETCH-NEXT: ntl.all
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 1(a0)
; RV64XMIPSPREFETCH-NEXT: ret
entry:
@@ -24,12 +26,14 @@ define void @prefetch_data_write(ptr noundef %ptr) nounwind {
; RV32XMIPSPREFETCH-LABEL: prefetch_data_write:
; RV32XMIPSPREFETCH: # %bb.0:
; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 512
+; RV32XMIPSPREFETCH-NEXT: ntl.all
; RV32XMIPSPREFETCH-NEXT: mips.pref 9, 0(a0)
; RV32XMIPSPREFETCH-NEXT: ret
;
; RV64XMIPSPREFETCH-LABEL: prefetch_data_write:
; RV64XMIPSPREFETCH: # %bb.0:
; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 512
+; RV64XMIPSPREFETCH-NEXT: ntl.all
; RV64XMIPSPREFETCH-NEXT: mips.pref 9, 0(a0)
; RV64XMIPSPREFETCH-NEXT: ret
%arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
@@ -57,6 +61,7 @@ define void @prefetch_frameindex_test_neg() nounwind {
; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16
; RV32XMIPSPREFETCH-NEXT: sub sp, sp, a0
; RV32XMIPSPREFETCH-NEXT: addi a0, sp, 524
+; RV32XMIPSPREFETCH-NEXT: ntl.all
; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
; RV32XMIPSPREFETCH-NEXT: lui a0, 1
; RV32XMIPSPREFETCH-NEXT: addi a0, a0, 16
@@ -69,6 +74,7 @@ define void @prefetch_frameindex_test_neg() nounwind {
; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16
; RV64XMIPSPREFETCH-NEXT: sub sp, sp, a0
; RV64XMIPSPREFETCH-NEXT: addi a0, sp, 524
+; RV64XMIPSPREFETCH-NEXT: ntl.all
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 0(a0)
; RV64XMIPSPREFETCH-NEXT: lui a0, 1
; RV64XMIPSPREFETCH-NEXT: addi a0, a0, 16
@@ -84,6 +90,7 @@ define void @prefetch_frameindex_test() nounwind {
; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
; RV32XMIPSPREFETCH: # %bb.0:
; RV32XMIPSPREFETCH-NEXT: addi sp, sp, -512
+; RV32XMIPSPREFETCH-NEXT: ntl.all
; RV32XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
; RV32XMIPSPREFETCH-NEXT: addi sp, sp, 512
; RV32XMIPSPREFETCH-NEXT: ret
@@ -91,6 +98,7 @@ define void @prefetch_frameindex_test() nounwind {
; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
; RV64XMIPSPREFETCH: # %bb.0:
; RV64XMIPSPREFETCH-NEXT: addi sp, sp, -512
+; RV64XMIPSPREFETCH-NEXT: ntl.all
; RV64XMIPSPREFETCH-NEXT: mips.pref 8, 32(sp)
; RV64XMIPSPREFETCH-NEXT: addi sp, sp, 512
; RV64XMIPSPREFETCH-NEXT: ret
>From 04829225516902726b64d0abf00ca6ab4eb3a4d5 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 5 Feb 2026 15:15:53 +0800
Subject: [PATCH 2/3] !fixup add test for int_riscv_pause without Zihintpause
---
llvm/test/CodeGen/RISCV/riscv-zihintpause.ll | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
index 46e06875efe7a..2df7983eb6ae7 100644
--- a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
@@ -1,12 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RVPAUSE
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s | FileCheck %s
+
+; The pause intrinsic is always available since pause is a HINT encoding.
define void @test_pause() {
-; RVPAUSE-LABEL: test_pause:
-; RVPAUSE: # %bb.0:
-; RVPAUSE-NEXT: pause
-; RVPAUSE-NEXT: ret
+; CHECK-LABEL: test_pause:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pause
+; CHECK-NEXT: ret
call void @llvm.riscv.pause()
ret void
}
>From 43d1b0c7f3921af5ad11bae43d6b6f7c562e9eaa Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng at sifive.com>
Date: Thu, 5 Feb 2026 15:32:53 +0800
Subject: [PATCH 3/3] !fixup simplify prefetch.ll test by merging identical
check prefixes
---
llvm/test/CodeGen/RISCV/prefetch.ll | 1808 +++++++--------------------
1 file changed, 448 insertions(+), 1360 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll
index 79cb5e0c6e85f..cc802a8304c07 100644
--- a/llvm/test/CodeGen/RISCV/prefetch.ll
+++ b/llvm/test/CodeGen/RISCV/prefetch.ll
@@ -1,736 +1,324 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32ZICBOP %s
-; RUN: llc -mtriple=riscv64 -mattr=+zicbop -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64ZICBOP %s
-; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+zihintntl -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64ZICBOPZIHINTNTL %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=NOZICBOP %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=NOZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s | FileCheck -check-prefix=ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicbop -verify-machineinstrs < %s | FileCheck -check-prefix=ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+zihintntl -verify-machineinstrs < %s | FileCheck -check-prefix=ZICBOP %s
define void @test_prefetch_read_locality_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_read_locality_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_write_locality_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_write_locality_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 0, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_instruction_locality_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 0, i32 0)
ret void
}
define void @test_prefetch_read_locality_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.pall
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.pall
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_read_locality_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.pall
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 1, i32 1)
ret void
}
define void @test_prefetch_write_locality_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.pall
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.pall
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_write_locality_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.pall
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 1, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.pall
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.pall
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_instruction_locality_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.pall
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 1, i32 0)
ret void
}
define void @test_prefetch_read_locality_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.p1
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.p1
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_read_locality_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.p1
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 1)
ret void
}
define void @test_prefetch_write_locality_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.p1
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.p1
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_write_locality_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.p1
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 2, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.p1
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.p1
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_instruction_locality_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.p1
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 0)
ret void
}
define void @test_prefetch_read_locality_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_read_locality_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 3, i32 1)
ret void
}
define void @test_prefetch_write_locality_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_write_locality_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 3, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_instruction_locality_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 3, i32 0)
ret void
}
define void @test_prefetch_offsetable_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 2016
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -2048
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 32
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -32(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -32
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_4(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_4:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_4:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_4:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, 32
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_4:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, 32
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_4:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 32
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_4:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_4:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, 32
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 2048
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_5(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_5:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_5:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_5:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, -1
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_5:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, -1
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_5:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_5:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_5:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, -1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -2049
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_6(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_6:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_6:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_6:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, 16
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_6:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, 16
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_6:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_6:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_6:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, 16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 16
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_7(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_7:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_7:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_7:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, -16
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_7:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, -16
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_7:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_7:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_7:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, -16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -16
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_9(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_9:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_9:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_9:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a1, 1
-; RV32ZICBOP-NEXT: add a0, a0, a1
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 64(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_9:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a1, 1
-; RV64ZICBOP-NEXT: add a0, a0, a1
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 64(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_9:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a1, 1
-; RV64ZICBOPZIHINTNTL-NEXT: add a0, a0, a1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 64(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_9:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_9:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a1, 1
+; ZICBOP-NEXT: add a0, a0, a1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 64(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 4160
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_8(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_8:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_8:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a1, 1048575
-; RV32ZICBOP-NEXT: add a0, a0, a1
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -64(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_8:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a1, 1048575
-; RV64ZICBOP-NEXT: add a0, a0, a1
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -64(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_8:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a1, 1048575
-; RV64ZICBOPZIHINTNTL-NEXT: add a0, a0, a1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -64(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_8:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_offsetable_8:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a1, 1048575
+; ZICBOP-NEXT: add a0, a0, a1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -64(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -4160
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_frameindex_0() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 0
@@ -739,64 +327,27 @@ define void @test_prefetch_frameindex_0() nounwind {
}
define void @test_prefetch_frameindex_1() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 16
-; RV32I-NEXT: sub sp, sp, a0
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 16
-; RV32I-NEXT: add sp, sp, a0
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addi a0, a0, 16
-; RV64I-NEXT: sub sp, sp, a0
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addi a0, a0, 16
-; RV64I-NEXT: add sp, sp, a0
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: addi a0, a0, 16
-; RV32ZICBOP-NEXT: sub sp, sp, a0
-; RV32ZICBOP-NEXT: addi a0, sp, 16
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: addi a0, a0, 16
-; RV32ZICBOP-NEXT: add sp, sp, a0
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: addi a0, a0, 16
-; RV64ZICBOP-NEXT: sub sp, sp, a0
-; RV64ZICBOP-NEXT: addi a0, sp, 16
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: addi a0, a0, 16
-; RV64ZICBOP-NEXT: add sp, sp, a0
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
-; RV64ZICBOPZIHINTNTL-NEXT: sub sp, sp, a0
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
-; RV64ZICBOPZIHINTNTL-NEXT: add sp, sp, a0
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: lui a0, 1
+; NOZICBOP-NEXT: addi a0, a0, 16
+; NOZICBOP-NEXT: sub sp, sp, a0
+; NOZICBOP-NEXT: lui a0, 1
+; NOZICBOP-NEXT: addi a0, a0, 16
+; NOZICBOP-NEXT: add sp, sp, a0
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: addi a0, a0, 16
+; ZICBOP-NEXT: sub sp, sp, a0
+; ZICBOP-NEXT: addi a0, sp, 16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: addi a0, a0, 16
+; ZICBOP-NEXT: add sp, sp, a0
+; ZICBOP-NEXT: ret
%data = alloca [1024 x i32], align 4
%ptr = bitcast ptr %data to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
@@ -804,44 +355,19 @@ define void @test_prefetch_frameindex_1() nounwind {
}
define void @test_prefetch_frameindex_2() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: addi a0, sp, 16
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: addi a0, sp, 16
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: addi a0, sp, 16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 4
@@ -850,44 +376,19 @@ define void @test_prefetch_frameindex_2() nounwind {
}
define void @test_prefetch_frameindex_3() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: addi a0, sp, -16
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: addi a0, sp, -16
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, -16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: addi a0, sp, -16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -4
@@ -896,41 +397,18 @@ define void @test_prefetch_frameindex_3() nounwind {
}
define void @test_prefetch_frameindex_4() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_4:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_4:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_4:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 32(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_4:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 32(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_4:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_4:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_4:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
@@ -939,41 +417,18 @@ define void @test_prefetch_frameindex_4() nounwind {
}
define void @test_prefetch_frameindex_5() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_5:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_5:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_5:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -32(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_5:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -32(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_5:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -32(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_5:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_5:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -32(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
@@ -982,41 +437,18 @@ define void @test_prefetch_frameindex_5() nounwind {
}
define void @test_prefetch_frameindex_6() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_6:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_6:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_6:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 2016(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_6:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 2016(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_6:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_6:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_6:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 504
@@ -1025,41 +457,18 @@ define void @test_prefetch_frameindex_6() nounwind {
}
define void @test_prefetch_frameindex_7() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_7:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_7:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_7:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -2048(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_7:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -2048(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_7:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_7:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_7:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -512
@@ -1068,44 +477,19 @@ define void @test_prefetch_frameindex_7() nounwind {
}
define void @test_prefetch_frameindex_8() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_8:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_8:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: addi a0, sp, 2020
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_8:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: addi a0, sp, 2020
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_8:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 2020
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_8:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_8:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: addi a0, sp, 2020
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 505
@@ -1114,47 +498,20 @@ define void @test_prefetch_frameindex_8() nounwind {
}
define void @test_prefetch_frameindex_9() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_9:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_9:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_9:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: mv a0, sp
-; RV32ZICBOP-NEXT: addi a0, a0, -4
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_9:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: mv a0, sp
-; RV64ZICBOP-NEXT: addi a0, a0, -4
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_9:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: mv a0, sp
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -4
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_9:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_frameindex_9:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: mv a0, sp
+; ZICBOP-NEXT: addi a0, a0, -4
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -513
@@ -1163,142 +520,62 @@ define void @test_prefetch_frameindex_9() nounwind {
}
define void @test_prefetch_constant_address_0() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_constant_address_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 4128 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_constant_address_1() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: addi a0, a0, 31
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: addi a0, a0, 31
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 31
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_constant_address_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: addi a0, a0, 31
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 4127 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_constant_address_2() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1048561
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1048561
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_constant_address_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1048561
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 18446744073709490208 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_constant_address_3() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1048561
-; RV32ZICBOP-NEXT: addi a0, a0, 31
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1048561
-; RV64ZICBOP-NEXT: addi a0, a0, 31
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 31
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_constant_address_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1048561
+; ZICBOP-NEXT: addi a0, a0, 31
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 18446744073709490207 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
@@ -1307,333 +584,144 @@ define void @test_prefetch_constant_address_3() nounwind {
@g = external global [1024 x i32], align 4
define void @test_prefetch_global_0() nounwind {
-; RV32I-LABEL: test_prefetch_global_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 0
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_1() nounwind {
-; RV32I-LABEL: test_prefetch_global_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g+16)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+16)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g+16)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+16)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+16)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+16)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g+16)
+; ZICBOP-NEXT: addi a0, a0, %lo(g+16)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 4
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_2() nounwind {
-; RV32I-LABEL: test_prefetch_global_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g-16)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-16)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g-16)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-16)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-16)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-16)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g-16)
+; ZICBOP-NEXT: addi a0, a0, %lo(g-16)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -4
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_3() nounwind {
-; RV32I-LABEL: test_prefetch_global_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 8
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_4() nounwind {
-; RV32I-LABEL: test_prefetch_global_4:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_4:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_4:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_4:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_4:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_4:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_4:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -32(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -8
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_5() nounwind {
-; RV32I-LABEL: test_prefetch_global_5:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_5:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_5:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_5:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_5:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_5:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_5:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 504
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_6() nounwind {
-; RV32I-LABEL: test_prefetch_global_6:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_6:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_6:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_6:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_6:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_6:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_6:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -512
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_7() nounwind {
-; RV32I-LABEL: test_prefetch_global_7:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_7:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_7:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g+2020)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_7:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g+2020)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_7:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+2020)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+2020)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_7:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_7:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g+2020)
+; ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 505
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_8() nounwind {
-; RV32I-LABEL: test_prefetch_global_8:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_8:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g-4)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-4)
-; RV32ZICBOP-NEXT: ntl.all
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_8:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g-4)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-4)
-; RV64ZICBOP-NEXT: ntl.all
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_8:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-4)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-4)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_8:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+; ZICBOP-LABEL: test_prefetch_global_8:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g-4)
+; ZICBOP-NEXT: addi a0, a0, %lo(g-4)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -513
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
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