[llvm] [X86] lower1BitShuffle - recognise a blend shuffle that can lower to AND/MASKZ pattern (PR #179717)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/179717

Part of the missed-optimisation mentioned on #179630 - if the shuffle is a blend with zero, then lower as a ISD::AND pattern

>From ae51d445ae1dbd1f8b72b822dc961a32a8b707e1 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Wed, 4 Feb 2026 17:59:40 +0000
Subject: [PATCH] [X86] lower1BitShuffle - recognise a blend shuffle that can
 lower to AND/MASKZ pattern

Part of the missed-optimisation mentioned on #179630 - if the shuffle is a blend with zero, then lower as a ISD::AND pattern
---
 llvm/lib/Target/X86/X86ISelLowering.cpp   | 10 ++++++++++
 llvm/test/CodeGen/X86/avx512bwvl-arith.ll |  9 +++------
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e86d478d1baa0..5cdbf87a12cfe 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18347,6 +18347,16 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
           DAG.getVectorShuffle(OpVT, DL, Op1, DAG.getUNDEF(OpVT), Mask), CC);
   }
 
+  // If this is a sequential shuffle with zero'd elements - then lower to AND.
+  bool IsBlendWithZero = all_of(enumerate(Mask), [&Zeroable](auto M) {
+    return Zeroable[M.index()] || (M.index() == M.value());
+  });
+  if (IsBlendWithZero) {
+    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
+    SDValue BlendMask = DAG.getConstant(~Zeroable, DL, IntVT);
+    return DAG.getNode(ISD::AND, DL, VT, V1, DAG.getBitcast(VT, BlendMask));
+  }
+
   MVT ExtVT;
   switch (VT.SimpleTy) {
   default:
diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
index 28ff1b3e2da0d..decab7b485c4d 100644
--- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
+++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll
@@ -239,15 +239,12 @@ define i16 @PR90356(<16 x i1> %a) {
 ; CHECK-LABEL: PR90356:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpsllw $7, %xmm0, %xmm0
-; CHECK-NEXT:    vpmovb2m %xmm0, %k1
-; CHECK-NEXT:    vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1
-; CHECK-NEXT:    movb $63, %al
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    movw $4095, %ax # imm = 0xFFF
 ; CHECK-NEXT:    kmovd %eax, %k1
-; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT:    vptestmd %zmm0, %zmm0, %k0
+; CHECK-NEXT:    vpcmpgtb %xmm0, %xmm1, %k0 {%k1}
 ; CHECK-NEXT:    kmovd %k0, %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %1 = shufflevector <16 x i1> %a, <16 x i1> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31>
   %2 = bitcast <16 x i1> %1 to i16